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EDAC/amd64: Document heterogeneous system enumeration
Document High Bandwidth Memory (HBM) and AMD heterogeneous system topology and enumeration. [ bp: Simplify and de-marketize, unify, massage. ] Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> Co-developed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230515113537.1052146-4-muralimk@amd.com
This commit is contained in:
Muralidhara M K
Borislav Petkov (AMD)
parent
c35977b00f
commit
4f3fa571a4
@ -106,6 +106,16 @@ will occupy those chip-select rows.
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This term is avoided because it is unclear when needing to distinguish
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between chip-select rows and socket sets.
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* High Bandwidth Memory (HBM)
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HBM is a new memory type with low power consumption and ultra-wide
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communication lanes. It uses vertically stacked memory chips (DRAM dies)
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interconnected by microscopic wires called "through-silicon vias," or
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TSVs.
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Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
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interconnect called the "interposer". Therefore, HBM's characteristics
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are nearly indistinguishable from on-chip integrated RAM.
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Memory Controllers
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------------------
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@ -176,3 +186,113 @@ nodes::
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the L1 and L2 directories would be "edac_device_block's"
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.. kernel-doc:: drivers/edac/edac_device.h
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Heterogeneous system support
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----------------------------
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An AMD heterogeneous system is built by connecting the data fabrics of
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both CPUs and GPUs via custom xGMI links. Thus, the data fabric on the
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GPU nodes can be accessed the same way as the data fabric on CPU nodes.
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The MI200 accelerators are data center GPUs. They have 2 data fabrics,
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and each GPU data fabric contains four Unified Memory Controllers (UMC).
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Each UMC contains eight channels. Each UMC channel controls one 128-bit
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HBM2e (2GB) channel (equivalent to 8 X 2GB ranks). This creates a total
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of 4096-bits of DRAM data bus.
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While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
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channel is interfacing 2GB of DRAM (represented as rank).
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Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
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GPU DF / GPU Node -> EDAC MC
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GPU UMC -> EDAC CSROW
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GPU UMC channel -> EDAC CHANNEL
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For example: a heterogeneous system with 1 AMD CPU is connected to
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4 MI200 (Aldebaran) GPUs using xGMI.
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Some more heterogeneous hardware details:
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- The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
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They have chip selects (csrows) and channels. However, the layouts are different
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for performance, physical layout, or other reasons.
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- CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the
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marketing speak. CPU has X memory channels, etc.
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- CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.
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- GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
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- GPU UMCs use 8 channels, So UMC channel = EDAC channel.
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The EDAC subsystem provides a mechanism to handle AMD heterogeneous
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systems by calling system specific ops for both CPUs and GPUs.
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AMD GPU nodes are enumerated in sequential order based on the PCI
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hierarchy, and the first GPU node is assumed to have a Node ID value
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following those of the CPU nodes after latter are fully populated::
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$ ls /sys/devices/system/edac/mc/
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mc0 - CPU MC node 0
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mc1 |
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mc2 |- GPU card[0] => node 0(mc1), node 1(mc2)
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mc3 |
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mc4 |- GPU card[1] => node 0(mc3), node 1(mc4)
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mc5 |
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mc6 |- GPU card[2] => node 0(mc5), node 1(mc6)
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mc7 |
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mc8 |- GPU card[3] => node 0(mc7), node 1(mc8)
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For example, a heterogeneous system with one AMD CPU is connected to
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four MI200 (Aldebaran) GPUs using xGMI. This topology can be represented
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via the following sysfs entries::
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/sys/devices/system/edac/mc/..
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CPU # CPU node
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├── mc 0
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GPU Nodes are enumerated sequentially after CPU nodes have been populated
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GPU card 1 # Each MI200 GPU has 2 nodes/mcs
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├── mc 1 # GPU node 0 == mc1, Each MC node has 4 UMCs/CSROWs
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│ ├── csrow 0 # UMC 0
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│ │ ├── channel 0 # Each UMC has 8 channels
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│ │ ├── channel 1 # size of each channel is 2 GB, so each UMC has 16 GB
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│ │ ├── channel 2
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│ │ ├── channel 3
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│ │ ├── channel 4
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│ │ ├── channel 5
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│ │ ├── channel 6
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│ │ ├── channel 7
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│ ├── csrow 1 # UMC 1
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│ │ ├── channel 0
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│ │ ├── ..
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│ │ ├── channel 7
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│ ├── .. ..
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│ ├── csrow 3 # UMC 3
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│ │ ├── channel 0
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│ │ ├── ..
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│ │ ├── channel 7
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│ ├── rank 0
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│ ├── .. ..
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│ ├── rank 31 # total 32 ranks/dimms from 4 UMCs
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├
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├── mc 2 # GPU node 1 == mc2
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│ ├── .. # each GPU has total 64 GB
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GPU card 2
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├── mc 3
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│ ├── ..
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├── mc 4
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│ ├── ..
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GPU card 3
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├── mc 5
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│ ├── ..
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├── mc 6
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│ ├── ..
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GPU card 4
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├── mc 7
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│ ├── ..
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├── mc 8
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│ ├── ..
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