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PCI: microchip: Add event irqchip field to host port and add PLDA irqchip
As the PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) shows, PLDA PCIe contains an interrupt controller. Microchip PolarFire PCIe event IRQs include PLDA interrupts and PolarFire additional interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. Microchip PolarFire PCIe additional interrupts require to write PolarFire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20240328091835.14797-16-minda.chen@starfivetech.com Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
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c7f6c72ae1
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@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
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.irq_unmask = mc_unmask_event_irq,
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};
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static u32 plda_hwirq_to_mask(int hwirq)
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{
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u32 mask;
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/* hwirq 23 - 0 are the same with register */
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if (hwirq < EVENT_PM_MSI_INT_INTX)
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mask = BIT(hwirq);
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else if (hwirq == EVENT_PM_MSI_INT_INTX)
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mask = PM_MSI_INT_INTX_MASK;
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else
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mask = BIT(hwirq + PCI_NUM_INTX - 1);
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return mask;
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}
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static void plda_ack_event_irq(struct irq_data *data)
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{
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struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
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writel_relaxed(plda_hwirq_to_mask(data->hwirq),
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port->bridge_addr + ISTATUS_LOCAL);
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}
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static void plda_mask_event_irq(struct irq_data *data)
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{
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struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
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u32 mask, val;
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mask = plda_hwirq_to_mask(data->hwirq);
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raw_spin_lock(&port->lock);
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val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
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val &= ~mask;
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writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
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raw_spin_unlock(&port->lock);
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}
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static void plda_unmask_event_irq(struct irq_data *data)
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{
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struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
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u32 mask, val;
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mask = plda_hwirq_to_mask(data->hwirq);
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raw_spin_lock(&port->lock);
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val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
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val |= mask;
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writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
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raw_spin_unlock(&port->lock);
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}
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static struct irq_chip plda_event_irq_chip = {
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.name = "PLDA PCIe EVENT",
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.irq_ack = plda_ack_event_irq,
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.irq_mask = plda_mask_event_irq,
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.irq_unmask = plda_unmask_event_irq,
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};
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static const struct plda_event_ops plda_event_ops = {
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.get_events = plda_get_events,
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};
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@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops = {
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static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
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struct plda_pcie_rp *port = (void *)domain->host_data;
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irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device *pdev,
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if (!port->event_ops)
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port->event_ops = &plda_event_ops;
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if (!port->event_irq_chip)
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port->event_irq_chip = &plda_event_irq_chip;
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ret = plda_pcie_init_irq_domains(port);
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if (ret) {
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dev_err(dev, "failed creating IRQ domains\n");
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@ -1038,6 +1101,7 @@ static int mc_platform_init(struct pci_config_window *cfg)
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return ret;
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port->plda.event_ops = &mc_event_ops;
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port->plda.event_irq_chip = &mc_event_irq_chip;
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/* Address translation is up; safe to enable interrupts */
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ret = plda_init_interrupts(pdev, &port->plda, &mc_event);
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@ -107,6 +107,8 @@ enum plda_int_event {
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#define PLDA_NUM_DMA_EVENTS 16
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#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX)
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#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI)
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#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
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/*
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@ -116,21 +118,22 @@ enum plda_int_event {
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* +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+
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* |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end |
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* +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+
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* bit 0-7 DMA interrupt end : reserved for vendor implement
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* bit 8-15 DMA error : reserved for vendor implement
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* 0: AXI post error (PLDA_AXI_POST_ERR)
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* 1: AXI fetch error (PLDA_AXI_FETCH_ERR)
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* 2: AXI discard error (PLDA_AXI_DISCARD_ERR)
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* 3: AXI doorbell (PLDA_PCIE_DOORBELL)
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* 4: PCIe post error (PLDA_PCIE_POST_ERR)
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* 5: PCIe fetch error (PLDA_PCIE_FETCH_ERR)
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* 6: PCIe discard error (PLDA_PCIE_DISCARD_ERR)
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* 7: PCIe doorbell (PLDA_PCIE_DOORBELL)
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* 8: 4 INTx interruts (PLDA_INTX)
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* 9: MSI interrupt (PLDA_MSI)
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* 10: AER event (PLDA_AER_EVENT)
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* 11: PM/LTR/Hotplug (PLDA_MISC_EVENTS)
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* 12: System error (PLDA_SYS_ERR)
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* event bit
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* 0-7 (0-7) DMA interrupt end : reserved for vendor implement
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* 8-15 (8-15) DMA error : reserved for vendor implement
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* 16 (16) AXI post error (PLDA_AXI_POST_ERR)
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* 17 (17) AXI fetch error (PLDA_AXI_FETCH_ERR)
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* 18 (18) AXI discard error (PLDA_AXI_DISCARD_ERR)
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* 19 (19) AXI doorbell (PLDA_PCIE_DOORBELL)
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* 20 (20) PCIe post error (PLDA_PCIE_POST_ERR)
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* 21 (21) PCIe fetch error (PLDA_PCIE_FETCH_ERR)
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* 22 (22) PCIe discard error (PLDA_PCIE_DISCARD_ERR)
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* 23 (23) PCIe doorbell (PLDA_PCIE_DOORBELL)
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* 24 (27-24) INTx interruts (PLDA_INTX)
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* 25 (28): MSI interrupt (PLDA_MSI)
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* 26 (29): AER event (PLDA_AER_EVENT)
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* 27 (30): PM/LTR/Hotplug (PLDA_MISC_EVENTS)
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* 28 (31): System error (PLDA_SYS_ERR)
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*/
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struct plda_pcie_rp;
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@ -155,6 +158,7 @@ struct plda_pcie_rp {
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raw_spinlock_t lock;
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struct plda_msi msi;
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const struct plda_event_ops *event_ops;
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const struct irq_chip *event_irq_chip;
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void __iomem *bridge_addr;
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int num_events;
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};
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