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Merge branch 'icc-qcs615' into icc-next

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Add interconnect dt-bindings and driver support for Qualcomm QCS615 SoC.

* icc-qcs615
  dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS615 SoC
  interconnect: qcom: add QCS615 interconnect provider driver

Link: https://lore.kernel.org/r/20240924143958.25-1-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2024-11-05 01:30:52 +02:00
commit 55aac0ea75
6 changed files with 1911 additions and 0 deletions
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73
Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml Normal file
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@ -0,0 +1,73 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,qcs615-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on QCS615
maintainers:
- Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
properties:
compatible:
enum:
- qcom,qcs615-aggre1-noc
- qcom,qcs615-camnoc-virt
- qcom,qcs615-config-noc
- qcom,qcs615-dc-noc
- qcom,qcs615-gem-noc
- qcom,qcs615-ipa-virt
- qcom,qcs615-mc-virt
- qcom,qcs615-mmss-noc
- qcom,qcs615-system-noc
reg:
maxItems: 1
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs615-camnoc-virt
- qcom,qcs615-ipa-virt
- qcom,qcs615-mc-virt
then:
properties:
reg: false
else:
required:
- reg
unevaluatedProperties: false
examples:
- |
gem_noc: interconnect@9680000 {
compatible = "qcom,qcs615-gem-noc";
reg = <0x9680000 0x3e200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-2 {
compatible = "qcom,qcs615-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

9
drivers/interconnect/qcom/Kconfig
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@ -105,6 +105,15 @@ config INTERCONNECT_QCOM_QCS404
This is a driver for the Qualcomm Network-on-Chip on qcs404-based
platforms.
config INTERCONNECT_QCOM_QCS615
tristate "Qualcomm QCS615 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on qcs615-based
platforms.
config INTERCONNECT_QCOM_QCS8300
tristate "Qualcomm QCS8300 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

2
drivers/interconnect/qcom/Makefile
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@ -15,6 +15,7 @@ qnoc-msm8996-objs := msm8996.o
icc-osm-l3-objs := osm-l3.o
qnoc-qcm2290-objs := qcm2290.o
qnoc-qcs404-objs := qcs404.o
qnoc-qcs615-objs := qcs615.o
qnoc-qcs8300-objs := qcs8300.o
qnoc-qdu1000-objs := qdu1000.o
icc-rpmh-obj := icc-rpmh.o
@ -53,6 +54,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS615) += qnoc-qcs615.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS8300) += qnoc-qcs8300.o
obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o

1563
drivers/interconnect/qcom/qcs615.c Normal file
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128
drivers/interconnect/qcom/qcs615.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H
#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H
#define QCS615_MASTER_A1NOC_CFG 1
#define QCS615_MASTER_A1NOC_SNOC 2
#define QCS615_MASTER_ANOC_PCIE_SNOC 3
#define QCS615_MASTER_APPSS_PROC 4
#define QCS615_MASTER_BLSP_1 5
#define QCS615_MASTER_CAMNOC_HF0 6
#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7
#define QCS615_MASTER_CAMNOC_HF1 8
#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9
#define QCS615_MASTER_CAMNOC_SF 10
#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11
#define QCS615_MASTER_CNOC_A2NOC 12
#define QCS615_MASTER_CNOC_DC_NOC 13
#define QCS615_MASTER_CNOC_MNOC_CFG 14
#define QCS615_MASTER_CRYPTO 15
#define QCS615_MASTER_EMAC_EVB 16
#define QCS615_MASTER_GEM_NOC_CFG 17
#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18
#define QCS615_MASTER_GEM_NOC_SNOC 19
#define QCS615_MASTER_GFX3D 20
#define QCS615_MASTER_GIC 21
#define QCS615_MASTER_GPU_TCU 22
#define QCS615_MASTER_IPA 23
#define QCS615_MASTER_IPA_CORE 24
#define QCS615_MASTER_LLCC 25
#define QCS615_MASTER_LPASS_ANOC 26
#define QCS615_MASTER_MDP0 27
#define QCS615_MASTER_MNOC_HF_MEM_NOC 28
#define QCS615_MASTER_MNOC_SF_MEM_NOC 29
#define QCS615_MASTER_PCIE 30
#define QCS615_MASTER_PIMEM 31
#define QCS615_MASTER_QDSS_BAM 32
#define QCS615_MASTER_QDSS_DAP 33
#define QCS615_MASTER_QDSS_ETR 34
#define QCS615_MASTER_QSPI 35
#define QCS615_MASTER_QUP_0 36
#define QCS615_MASTER_ROTATOR 37
#define QCS615_MASTER_SDCC_1 38
#define QCS615_MASTER_SDCC_2 39
#define QCS615_MASTER_SNOC_CFG 40
#define QCS615_MASTER_SNOC_CNOC 41
#define QCS615_MASTER_SNOC_GC_MEM_NOC 42
#define QCS615_MASTER_SNOC_SF_MEM_NOC 43
#define QCS615_MASTER_SPDM 44
#define QCS615_MASTER_SYS_TCU 45
#define QCS615_MASTER_UFS_MEM 46
#define QCS615_MASTER_USB2 47
#define QCS615_MASTER_USB3_0 48
#define QCS615_MASTER_VIDEO_P0 49
#define QCS615_MASTER_VIDEO_PROC 50
#define QCS615_SLAVE_A1NOC_CFG 51
#define QCS615_SLAVE_A1NOC_SNOC 52
#define QCS615_SLAVE_AHB2PHY_EAST 53
#define QCS615_SLAVE_AHB2PHY_WEST 54
#define QCS615_SLAVE_ANOC_PCIE_SNOC 55
#define QCS615_SLAVE_AOP 56
#define QCS615_SLAVE_AOSS 57
#define QCS615_SLAVE_APPSS 58
#define QCS615_SLAVE_CAMERA_CFG 59
#define QCS615_SLAVE_CAMNOC_UNCOMP 60
#define QCS615_SLAVE_CLK_CTL 61
#define QCS615_SLAVE_CNOC_A2NOC 62
#define QCS615_SLAVE_CNOC_DDRSS 63
#define QCS615_SLAVE_CNOC_MNOC_CFG 64
#define QCS615_SLAVE_CRYPTO_0_CFG 65
#define QCS615_SLAVE_DC_NOC_GEMNOC 66
#define QCS615_SLAVE_DISPLAY_CFG 67
#define QCS615_SLAVE_EBI1 68
#define QCS615_SLAVE_EMAC_AVB_CFG 69
#define QCS615_SLAVE_GEM_NOC_SNOC 70
#define QCS615_SLAVE_GFX3D_CFG 71
#define QCS615_SLAVE_GLM 72
#define QCS615_SLAVE_IMEM 73
#define QCS615_SLAVE_IMEM_CFG 74
#define QCS615_SLAVE_IPA_CFG 75
#define QCS615_SLAVE_IPA_CORE 76
#define QCS615_SLAVE_LLCC 77
#define QCS615_SLAVE_LLCC_CFG 78
#define QCS615_SLAVE_LPASS_SNOC 79
#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80
#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81
#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82
#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83
#define QCS615_SLAVE_PCIE_0 84
#define QCS615_SLAVE_PCIE_CFG 85
#define QCS615_SLAVE_PIMEM 86
#define QCS615_SLAVE_PIMEM_CFG 87
#define QCS615_SLAVE_PRNG 88
#define QCS615_SLAVE_QDSS_CFG 89
#define QCS615_SLAVE_QDSS_STM 90
#define QCS615_SLAVE_QSPI 91
#define QCS615_SLAVE_QUP_0 92
#define QCS615_SLAVE_QUP_1 93
#define QCS615_SLAVE_RBCPR_CX_CFG 94
#define QCS615_SLAVE_RBCPR_MX_CFG 95
#define QCS615_SLAVE_SDCC_1 96
#define QCS615_SLAVE_SDCC_2 97
#define QCS615_SLAVE_SERVICE_A2NOC 98
#define QCS615_SLAVE_SERVICE_CNOC 99
#define QCS615_SLAVE_SERVICE_GEM_NOC 100
#define QCS615_SLAVE_SERVICE_MNOC 101
#define QCS615_SLAVE_SERVICE_SNOC 102
#define QCS615_SLAVE_SNOC_CFG 103
#define QCS615_SLAVE_SNOC_CNOC 104
#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105
#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106
#define QCS615_SLAVE_SPDM_WRAPPER 107
#define QCS615_SLAVE_TCSR 108
#define QCS615_SLAVE_TCU 109
#define QCS615_SLAVE_TLMM_EAST 110
#define QCS615_SLAVE_TLMM_SOUTH 111
#define QCS615_SLAVE_TLMM_WEST 112
#define QCS615_SLAVE_UFS_MEM_CFG 113
#define QCS615_SLAVE_USB2 114
#define QCS615_SLAVE_USB3 115
#define QCS615_SLAVE_VENUS_CFG 116
#define QCS615_SLAVE_VSENSE_CTRL_CFG 117
#endif

136
include/dt-bindings/interconnect/qcom,qcs615-rpmh.h Normal file
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@ -0,0 +1,136 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS615_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS615_H
#define MASTER_A1NOC_CFG 1
#define MASTER_QDSS_BAM 2
#define MASTER_QSPI 3
#define MASTER_QUP_0 4
#define MASTER_BLSP_1 5
#define MASTER_CNOC_A2NOC 6
#define MASTER_CRYPTO 7
#define MASTER_IPA 8
#define MASTER_EMAC_EVB 9
#define MASTER_PCIE 10
#define MASTER_QDSS_ETR 11
#define MASTER_SDCC_1 12
#define MASTER_SDCC_2 13
#define MASTER_UFS_MEM 14
#define MASTER_USB2 15
#define MASTER_USB3_0 16
#define SLAVE_A1NOC_SNOC 17
#define SLAVE_LPASS_SNOC 18
#define SLAVE_ANOC_PCIE_SNOC 19
#define SLAVE_SERVICE_A2NOC 20
#define MASTER_CAMNOC_HF0_UNCOMP 1
#define MASTER_CAMNOC_HF1_UNCOMP 2
#define MASTER_CAMNOC_SF_UNCOMP 3
#define SLAVE_CAMNOC_UNCOMP 4
#define MASTER_SPDM 1
#define MASTER_SNOC_CNOC 2
#define MASTER_QDSS_DAP 3
#define SLAVE_A1NOC_CFG 4
#define SLAVE_AHB2PHY_EAST 5
#define SLAVE_AHB2PHY_WEST 6
#define SLAVE_AOP 7
#define SLAVE_AOSS 8
#define SLAVE_CAMERA_CFG 9
#define SLAVE_CLK_CTL 10
#define SLAVE_RBCPR_CX_CFG 11
#define SLAVE_RBCPR_MX_CFG 12
#define SLAVE_CRYPTO_0_CFG 13
#define SLAVE_CNOC_DDRSS 14
#define SLAVE_DISPLAY_CFG 15
#define SLAVE_EMAC_AVB_CFG 16
#define SLAVE_GLM 17
#define SLAVE_GFX3D_CFG 18
#define SLAVE_IMEM_CFG 19
#define SLAVE_IPA_CFG 20
#define SLAVE_CNOC_MNOC_CFG 21
#define SLAVE_PCIE_CFG 22
#define SLAVE_PIMEM_CFG 23
#define SLAVE_PRNG 24
#define SLAVE_QDSS_CFG 25
#define SLAVE_QSPI 26
#define SLAVE_QUP_0 27
#define SLAVE_QUP_1 28
#define SLAVE_SDCC_1 29
#define SLAVE_SDCC_2 30
#define SLAVE_SNOC_CFG 31
#define SLAVE_SPDM_WRAPPER 32
#define SLAVE_TCSR 33
#define SLAVE_TLMM_EAST 34
#define SLAVE_TLMM_SOUTH 35
#define SLAVE_TLMM_WEST 36
#define SLAVE_UFS_MEM_CFG 37
#define SLAVE_USB2 38
#define SLAVE_USB3 39
#define SLAVE_VENUS_CFG 40
#define SLAVE_VSENSE_CTRL_CFG 41
#define SLAVE_CNOC_A2NOC 42
#define SLAVE_SERVICE_CNOC 43
#define MASTER_CNOC_DC_NOC 1
#define SLAVE_DC_NOC_GEMNOC 2
#define SLAVE_LLCC_CFG 3
#define MASTER_APPSS_PROC 1
#define MASTER_GPU_TCU 2
#define MASTER_SYS_TCU 3
#define MASTER_GEM_NOC_CFG 4
#define MASTER_GFX3D 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_SNOC_GC_MEM_NOC 8
#define MASTER_SNOC_SF_MEM_NOC 9
#define SLAVE_MSS_PROC_MS_MPU_CFG 10
#define SLAVE_GEM_NOC_SNOC 11
#define SLAVE_LLCC 12
#define SLAVE_MEM_NOC_PCIE_SNOC 13
#define SLAVE_SERVICE_GEM_NOC 14
#define MASTER_IPA_CORE 1
#define SLAVE_IPA_CORE 2
#define MASTER_LLCC 1
#define SLAVE_EBI1 2
#define MASTER_CNOC_MNOC_CFG 1
#define MASTER_CAMNOC_HF0 2
#define MASTER_CAMNOC_HF1 3
#define MASTER_CAMNOC_SF 4
#define MASTER_MDP0 5
#define MASTER_ROTATOR 6
#define MASTER_VIDEO_P0 7
#define MASTER_VIDEO_PROC 8
#define SLAVE_MNOC_SF_MEM_NOC 9
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_SERVICE_MNOC 11
#define MASTER_SNOC_CFG 1
#define MASTER_A1NOC_SNOC 2
#define MASTER_GEM_NOC_SNOC 3
#define MASTER_GEM_NOC_PCIE_SNOC 4
#define MASTER_LPASS_ANOC 5
#define MASTER_ANOC_PCIE_SNOC 6
#define MASTER_PIMEM 7
#define MASTER_GIC 8
#define SLAVE_APPSS 9
#define SLAVE_SNOC_CNOC 10
#define SLAVE_SNOC_GEM_NOC_SF 11
#define SLAVE_SNOC_MEM_NOC_GC 12
#define SLAVE_IMEM 13
#define SLAVE_PIMEM 14
#define SLAVE_SERVICE_SNOC 15
#define SLAVE_PCIE_0 16
#define SLAVE_QDSS_STM 17
#define SLAVE_TCU 18
#endif