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ASoC: sun4i-codec: Add support for different DAC FIFOC addresses to quirks
The Allwinner H616 SoC uses a different register address to control the output FIFO. Allow this to be specified separately from the ADC FIFO control register. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Ryan Walklin <ryan@testtoast.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Philippe Simons <simons.philippe@gmail.com> Link: https://patch.msgid.link/20241023075917.186835-4-ryan@testtoast.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Marcus Cooper
Mark Brown
parent
a77e6c12cd
commit
5836a9d2ca
@ -238,6 +238,8 @@ struct sun4i_codec {
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/* ADC_FIFOC register is at different offset on different SoCs */
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struct regmap_field *reg_adc_fifoc;
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/* DAC_FIFOC register is at different offset on different SoCs */
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struct regmap_field *reg_dac_fifoc;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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@ -246,19 +248,19 @@ struct sun4i_codec {
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static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
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{
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/* Flush TX FIFO */
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regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
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regmap_field_set_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
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/* Enable DAC DRQ */
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regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
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regmap_field_set_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
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}
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static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
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{
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/* Disable DAC DRQ */
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regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
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regmap_field_clear_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
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}
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static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
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@ -356,13 +358,13 @@ static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
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u32 val;
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/* Flush the TX FIFO */
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regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
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regmap_field_set_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
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/* Set TX FIFO Empty Trigger Level */
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regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
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0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
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regmap_field_update_bits(scodec->reg_dac_fifoc,
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0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
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0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
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if (substream->runtime->rate > 32000)
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/* Use 64 bits FIR filter */
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@ -371,13 +373,13 @@ static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
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/* Use 32 bits FIR filter */
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val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
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regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
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val);
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regmap_field_update_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
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val);
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/* Send zeros when we have an underrun */
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regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
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regmap_field_clear_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
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return 0;
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};
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@ -510,9 +512,9 @@ static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
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u32 val;
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/* Set DAC sample rate */
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regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
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hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
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regmap_field_update_bits(scodec->reg_dac_fifoc,
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7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
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hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
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/* Set the number of channels we want to use */
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if (params_channels(params) == 1)
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@ -520,27 +522,27 @@ static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
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else
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val = 0;
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regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
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val);
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regmap_field_update_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
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val);
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/* Set the number of sample bits to either 16 or 24 bits */
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if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
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regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
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regmap_field_set_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
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/* Set TX FIFO mode to padding the LSBs with 0 */
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regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
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regmap_field_clear_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
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scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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} else {
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regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
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regmap_field_clear_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
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/* Set TX FIFO mode to repeat the MSB */
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regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
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regmap_field_set_bits(scodec->reg_dac_fifoc,
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BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
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scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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}
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@ -587,8 +589,8 @@ static int sun4i_codec_startup(struct snd_pcm_substream *substream,
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* Stop issuing DRQ when we have room for less than 16 samples
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* in our TX FIFO
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*/
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regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
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regmap_field_set_bits(scodec->reg_dac_fifoc,
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3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
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return clk_prepare_enable(scodec->clk_module);
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}
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@ -1565,6 +1567,7 @@ struct sun4i_codec_quirks {
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const struct snd_soc_component_driver *codec;
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struct snd_soc_card * (*create_card)(struct device *dev);
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struct reg_field reg_adc_fifoc; /* used for regmap_field */
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struct reg_field reg_dac_fifoc; /* used for regmap_field */
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unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
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unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
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bool has_reset;
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@ -1575,6 +1578,7 @@ static const struct sun4i_codec_quirks sun4i_codec_quirks = {
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.codec = &sun4i_codec_codec,
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.create_card = sun4i_codec_create_card,
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.reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
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.reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
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.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
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.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
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};
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@ -1584,6 +1588,7 @@ static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
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.codec = &sun6i_codec_codec,
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.create_card = sun6i_codec_create_card,
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.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
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.reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
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.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
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.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
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.has_reset = true,
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@ -1594,6 +1599,7 @@ static const struct sun4i_codec_quirks sun7i_codec_quirks = {
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.codec = &sun7i_codec_codec,
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.create_card = sun4i_codec_create_card,
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.reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
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.reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
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.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
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.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
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};
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@ -1603,6 +1609,7 @@ static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
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.codec = &sun8i_a23_codec_codec,
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.create_card = sun8i_a23_codec_create_card,
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.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
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.reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
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.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
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.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
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.has_reset = true,
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@ -1618,6 +1625,7 @@ static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
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.codec = &sun8i_a23_codec_codec,
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.create_card = sun8i_h3_codec_create_card,
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.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
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.reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
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.reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
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.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
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.has_reset = true,
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@ -1632,6 +1640,7 @@ static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = {
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.codec = &sun8i_a23_codec_codec,
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.create_card = sun8i_v3s_codec_create_card,
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.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
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.reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
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.reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
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.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
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.has_reset = true,
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@ -1739,6 +1748,16 @@ static int sun4i_codec_probe(struct platform_device *pdev)
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return ret;
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}
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scodec->reg_dac_fifoc = devm_regmap_field_alloc(&pdev->dev,
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scodec->regmap,
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quirks->reg_dac_fifoc);
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if (IS_ERR(scodec->reg_dac_fifoc)) {
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ret = PTR_ERR(scodec->reg_dac_fifoc);
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dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
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ret);
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return ret;
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}
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/* Enable the bus clock */
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if (clk_prepare_enable(scodec->clk_apb)) {
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dev_err(&pdev->dev, "Failed to enable the APB clock\n");
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