mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-17 18:56:24 +00:00
dl2k: stop using net_device.{base_addr, irq} and convert to __iomem.
The eeprom registers always use the same PCI bar whereas the general registers may either use the same mapping as the eeprom registers or a different one. It is thus possible to simplify parse_eeprom(). Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
This commit is contained in:
Francois Romieu
parent
65712ec016
commit
5e3cc4e3aa
@ -16,6 +16,13 @@
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#include "dl2k.h"
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#include <linux/dma-mapping.h>
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#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
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#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
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#define dw8(reg, val) iowrite8(val, ioaddr + (reg))
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#define dr32(reg) ioread32(ioaddr + (reg))
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#define dr16(reg) ioread16(ioaddr + (reg))
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#define dr8(reg) ioread8(ioaddr + (reg))
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static char version[] __devinitdata =
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KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
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#define MAX_UNITS 8
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@ -49,8 +56,13 @@ module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
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/* Enable the default interrupts */
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#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
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UpdateStats | LinkEvent)
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#define EnableInt() \
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writew(DEFAULT_INTR, ioaddr + IntEnable)
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static void dl2k_enable_int(struct netdev_private *np)
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{
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void __iomem *ioaddr = np->ioaddr;
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dw16(IntEnable, DEFAULT_INTR);
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}
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static const int max_intrloop = 50;
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static const int multicast_filter_limit = 0x40;
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@ -73,7 +85,7 @@ static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
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static int rio_close (struct net_device *dev);
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static int find_miiphy (struct net_device *dev);
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static int parse_eeprom (struct net_device *dev);
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static int read_eeprom (long ioaddr, int eep_addr);
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static int read_eeprom (struct netdev_private *, int eep_addr);
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static int mii_wait_link (struct net_device *dev, int wait);
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static int mii_set_media (struct net_device *dev);
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static int mii_get_media (struct net_device *dev);
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@ -106,7 +118,7 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
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static int card_idx;
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int chip_idx = ent->driver_data;
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int err, irq;
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long ioaddr;
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void __iomem *ioaddr;
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static int version_printed;
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void *ring_space;
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dma_addr_t ring_dma;
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@ -124,26 +136,29 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
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goto err_out_disable;
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pci_set_master (pdev);
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err = -ENOMEM;
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dev = alloc_etherdev (sizeof (*np));
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if (!dev) {
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err = -ENOMEM;
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if (!dev)
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goto err_out_res;
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}
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SET_NETDEV_DEV(dev, &pdev->dev);
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#ifdef MEM_MAPPING
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ioaddr = pci_resource_start (pdev, 1);
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ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
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if (!ioaddr) {
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err = -ENOMEM;
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goto err_out_dev;
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}
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#else
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ioaddr = pci_resource_start (pdev, 0);
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#endif
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dev->base_addr = ioaddr;
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dev->irq = irq;
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np = netdev_priv(dev);
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/* IO registers range. */
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ioaddr = pci_iomap(pdev, 0, 0);
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if (!ioaddr)
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goto err_out_dev;
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np->eeprom_addr = ioaddr;
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#ifdef MEM_MAPPING
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/* MM registers range. */
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ioaddr = pci_iomap(pdev, 1, 0);
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if (!ioaddr)
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goto err_out_iounmap;
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#endif
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np->ioaddr = ioaddr;
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np->chip_id = chip_idx;
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np->pdev = pdev;
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spin_lock_init (&np->tx_lock);
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@ -239,7 +254,7 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
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goto err_out_unmap_rx;
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/* Fiber device? */
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np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
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np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
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np->link_status = 0;
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/* Set media and reset PHY */
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if (np->phy_media) {
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@ -276,22 +291,20 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
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printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
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return 0;
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err_out_unmap_rx:
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err_out_unmap_rx:
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pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
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err_out_unmap_tx:
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err_out_unmap_tx:
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pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
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err_out_iounmap:
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err_out_iounmap:
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#ifdef MEM_MAPPING
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iounmap ((void *) ioaddr);
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err_out_dev:
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pci_iounmap(pdev, np->ioaddr);
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#endif
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pci_iounmap(pdev, np->eeprom_addr);
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err_out_dev:
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free_netdev (dev);
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err_out_res:
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err_out_res:
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pci_release_regions (pdev);
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err_out_disable:
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err_out_disable:
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pci_disable_device (pdev);
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return err;
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}
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@ -299,11 +312,9 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
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static int
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find_miiphy (struct net_device *dev)
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{
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struct netdev_private *np = netdev_priv(dev);
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int i, phy_found = 0;
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struct netdev_private *np;
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long ioaddr;
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np = netdev_priv(dev);
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ioaddr = dev->base_addr;
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np->phy_addr = 1;
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for (i = 31; i >= 0; i--) {
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@ -323,26 +334,19 @@ find_miiphy (struct net_device *dev)
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static int
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parse_eeprom (struct net_device *dev)
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{
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struct netdev_private *np = netdev_priv(dev);
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void __iomem *ioaddr = np->ioaddr;
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int i, j;
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long ioaddr = dev->base_addr;
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u8 sromdata[256];
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u8 *psib;
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u32 crc;
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PSROM_t psrom = (PSROM_t) sromdata;
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struct netdev_private *np = netdev_priv(dev);
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int cid, next;
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#ifdef MEM_MAPPING
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ioaddr = pci_resource_start (np->pdev, 0);
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#endif
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/* Read eeprom */
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for (i = 0; i < 128; i++) {
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((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
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}
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#ifdef MEM_MAPPING
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ioaddr = dev->base_addr;
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#endif
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for (i = 0; i < 128; i++)
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((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
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if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
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/* Check CRC */
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crc = ~ether_crc_le (256 - 4, sromdata);
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@ -378,8 +382,7 @@ parse_eeprom (struct net_device *dev)
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return 0;
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case 2: /* Duplex Polarity */
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np->duplex_polarity = psib[i];
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writeb (readb (ioaddr + PhyCtrl) | psib[i],
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ioaddr + PhyCtrl);
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dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
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break;
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case 3: /* Wake Polarity */
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np->wake_polarity = psib[i];
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@ -407,59 +410,57 @@ static int
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rio_open (struct net_device *dev)
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{
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struct netdev_private *np = netdev_priv(dev);
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long ioaddr = dev->base_addr;
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void __iomem *ioaddr = np->ioaddr;
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const int irq = np->pdev->irq;
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int i;
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u16 macctrl;
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i = request_irq (dev->irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
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i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
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if (i)
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return i;
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/* Reset all logic functions */
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writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
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ioaddr + ASICCtrl + 2);
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dw16(ASICCtrl + 2,
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GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
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mdelay(10);
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/* DebugCtrl bit 4, 5, 9 must set */
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writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
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dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
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/* Jumbo frame */
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if (np->jumbo != 0)
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writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
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dw16(MaxFrameSize, MAX_JUMBO+14);
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alloc_list (dev);
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/* Get station address */
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for (i = 0; i < 6; i++)
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writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
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dw8(StationAddr0 + i, dev->dev_addr[i]);
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set_multicast (dev);
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if (np->coalesce) {
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writel (np->rx_coalesce | np->rx_timeout << 16,
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ioaddr + RxDMAIntCtrl);
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dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
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}
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/* Set RIO to poll every N*320nsec. */
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writeb (0x20, ioaddr + RxDMAPollPeriod);
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writeb (0xff, ioaddr + TxDMAPollPeriod);
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writeb (0x30, ioaddr + RxDMABurstThresh);
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writeb (0x30, ioaddr + RxDMAUrgentThresh);
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writel (0x0007ffff, ioaddr + RmonStatMask);
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dw8(RxDMAPollPeriod, 0x20);
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dw8(TxDMAPollPeriod, 0xff);
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dw8(RxDMABurstThresh, 0x30);
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dw8(RxDMAUrgentThresh, 0x30);
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dw32(RmonStatMask, 0x0007ffff);
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/* clear statistics */
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clear_stats (dev);
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/* VLAN supported */
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if (np->vlan) {
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/* priority field in RxDMAIntCtrl */
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writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
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ioaddr + RxDMAIntCtrl);
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dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
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/* VLANId */
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writew (np->vlan, ioaddr + VLANId);
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dw16(VLANId, np->vlan);
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/* Length/Type should be 0x8100 */
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writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
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dw32(VLANTag, 0x8100 << 16 | np->vlan);
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/* Enable AutoVLANuntagging, but disable AutoVLANtagging.
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VLAN information tagged by TFC' VID, CFI fields. */
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writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
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ioaddr + MACCtrl);
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dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
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}
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init_timer (&np->timer);
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@ -469,20 +470,18 @@ rio_open (struct net_device *dev)
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add_timer (&np->timer);
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/* Start Tx/Rx */
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writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
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ioaddr + MACCtrl);
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dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
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macctrl = 0;
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macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
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macctrl |= (np->full_duplex) ? DuplexSelect : 0;
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macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
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macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
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writew(macctrl, ioaddr + MACCtrl);
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dw16(MACCtrl, macctrl);
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netif_start_queue (dev);
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/* Enable default interrupts */
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EnableInt ();
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dl2k_enable_int(np);
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return 0;
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}
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@ -533,10 +532,11 @@ rio_timer (unsigned long data)
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static void
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rio_tx_timeout (struct net_device *dev)
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{
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long ioaddr = dev->base_addr;
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struct netdev_private *np = netdev_priv(dev);
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void __iomem *ioaddr = np->ioaddr;
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printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
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dev->name, readl (ioaddr + TxStatus));
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dev->name, dr32(TxStatus));
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rio_free_tx(dev, 0);
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dev->if_port = 0;
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dev->trans_start = jiffies; /* prevent tx timeout */
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@ -547,6 +547,7 @@ static void
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alloc_list (struct net_device *dev)
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{
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struct netdev_private *np = netdev_priv(dev);
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void __iomem *ioaddr = np->ioaddr;
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int i;
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np->cur_rx = np->cur_tx = 0;
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@ -594,24 +595,23 @@ alloc_list (struct net_device *dev)
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}
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/* Set RFDListPtr */
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writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
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writel (0, dev->base_addr + RFDListPtr1);
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dw32(RFDListPtr0, np->rx_ring_dma);
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dw32(RFDListPtr1, 0);
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}
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static netdev_tx_t
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start_xmit (struct sk_buff *skb, struct net_device *dev)
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{
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struct netdev_private *np = netdev_priv(dev);
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void __iomem *ioaddr = np->ioaddr;
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struct netdev_desc *txdesc;
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unsigned entry;
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u32 ioaddr;
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u64 tfc_vlan_tag = 0;
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if (np->link_status == 0) { /* Link Down */
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dev_kfree_skb(skb);
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return NETDEV_TX_OK;
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}
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ioaddr = dev->base_addr;
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entry = np->cur_tx % TX_RING_SIZE;
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np->tx_skbuff[entry] = skb;
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txdesc = &np->tx_ring[entry];
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@ -646,9 +646,9 @@ start_xmit (struct sk_buff *skb, struct net_device *dev)
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(1 << FragCountShift));
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/* TxDMAPollNow */
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writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
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dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
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/* Schedule ISR */
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writel(10000, ioaddr + CountDown);
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dw32(CountDown, 10000);
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np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
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if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
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< TX_QUEUE_LEN - 1 && np->speed != 10) {
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@ -658,10 +658,10 @@ start_xmit (struct sk_buff *skb, struct net_device *dev)
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}
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/* The first TFDListPtr */
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if (readl (dev->base_addr + TFDListPtr0) == 0) {
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writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
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dev->base_addr + TFDListPtr0);
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writel (0, dev->base_addr + TFDListPtr1);
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if (!dr32(TFDListPtr0)) {
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dw32(TFDListPtr0, np->tx_ring_dma +
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entry * sizeof (struct netdev_desc));
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dw32(TFDListPtr1, 0);
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}
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return NETDEV_TX_OK;
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@ -671,17 +671,15 @@ static irqreturn_t
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rio_interrupt (int irq, void *dev_instance)
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{
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struct net_device *dev = dev_instance;
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struct netdev_private *np;
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struct netdev_private *np = netdev_priv(dev);
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void __iomem *ioaddr = np->ioaddr;
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unsigned int_status;
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long ioaddr;
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int cnt = max_intrloop;
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int handled = 0;
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ioaddr = dev->base_addr;
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np = netdev_priv(dev);
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while (1) {
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int_status = readw (ioaddr + IntStatus);
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writew (int_status, ioaddr + IntStatus);
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int_status = dr16(IntStatus);
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dw16(IntStatus, int_status);
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int_status &= DEFAULT_INTR;
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if (int_status == 0 || --cnt < 0)
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break;
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@ -692,7 +690,7 @@ rio_interrupt (int irq, void *dev_instance)
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/* TxDMAComplete interrupt */
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if ((int_status & (TxDMAComplete|IntRequested))) {
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int tx_status;
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tx_status = readl (ioaddr + TxStatus);
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tx_status = dr32(TxStatus);
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if (tx_status & 0x01)
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tx_error (dev, tx_status);
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/* Free used tx skbuffs */
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@ -705,7 +703,7 @@ rio_interrupt (int irq, void *dev_instance)
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rio_error (dev, int_status);
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}
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if (np->cur_tx != np->old_tx)
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writel (100, ioaddr + CountDown);
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dw32(CountDown, 100);
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return IRQ_RETVAL(handled);
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}
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@ -765,13 +763,11 @@ rio_free_tx (struct net_device *dev, int irq)
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static void
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tx_error (struct net_device *dev, int tx_status)
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{
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struct netdev_private *np;
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long ioaddr = dev->base_addr;
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struct netdev_private *np = netdev_priv(dev);
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void __iomem *ioaddr = np->ioaddr;
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int frame_id;
|
||||
int i;
|
||||
|
||||
np = netdev_priv(dev);
|
||||
|
||||
frame_id = (tx_status & 0xffff0000);
|
||||
printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
|
||||
dev->name, tx_status, frame_id);
|
||||
@ -779,23 +775,21 @@ tx_error (struct net_device *dev, int tx_status)
|
||||
/* Ttransmit Underrun */
|
||||
if (tx_status & 0x10) {
|
||||
np->stats.tx_fifo_errors++;
|
||||
writew (readw (ioaddr + TxStartThresh) + 0x10,
|
||||
ioaddr + TxStartThresh);
|
||||
dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
|
||||
/* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
|
||||
writew (TxReset | DMAReset | FIFOReset | NetworkReset,
|
||||
ioaddr + ASICCtrl + 2);
|
||||
dw16(ASICCtrl + 2,
|
||||
TxReset | DMAReset | FIFOReset | NetworkReset);
|
||||
/* Wait for ResetBusy bit clear */
|
||||
for (i = 50; i > 0; i--) {
|
||||
if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
|
||||
if (!(dr16(ASICCtrl + 2) & ResetBusy))
|
||||
break;
|
||||
mdelay (1);
|
||||
}
|
||||
rio_free_tx (dev, 1);
|
||||
/* Reset TFDListPtr */
|
||||
writel (np->tx_ring_dma +
|
||||
np->old_tx * sizeof (struct netdev_desc),
|
||||
dev->base_addr + TFDListPtr0);
|
||||
writel (0, dev->base_addr + TFDListPtr1);
|
||||
dw32(TFDListPtr0, np->tx_ring_dma +
|
||||
np->old_tx * sizeof (struct netdev_desc));
|
||||
dw32(TFDListPtr1, 0);
|
||||
|
||||
/* Let TxStartThresh stay default value */
|
||||
}
|
||||
@ -803,10 +797,10 @@ tx_error (struct net_device *dev, int tx_status)
|
||||
if (tx_status & 0x04) {
|
||||
np->stats.tx_fifo_errors++;
|
||||
/* TxReset and clear FIFO */
|
||||
writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
|
||||
dw16(ASICCtrl + 2, TxReset | FIFOReset);
|
||||
/* Wait reset done */
|
||||
for (i = 50; i > 0; i--) {
|
||||
if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
|
||||
if (!(dr16(ASICCtrl + 2) & ResetBusy))
|
||||
break;
|
||||
mdelay (1);
|
||||
}
|
||||
@ -821,7 +815,7 @@ tx_error (struct net_device *dev, int tx_status)
|
||||
np->stats.collisions++;
|
||||
#endif
|
||||
/* Restart the Tx */
|
||||
writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
|
||||
dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -931,8 +925,8 @@ receive_packet (struct net_device *dev)
|
||||
static void
|
||||
rio_error (struct net_device *dev, int int_status)
|
||||
{
|
||||
long ioaddr = dev->base_addr;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
u16 macctrl;
|
||||
|
||||
/* Link change event */
|
||||
@ -954,7 +948,7 @@ rio_error (struct net_device *dev, int int_status)
|
||||
TxFlowControlEnable : 0;
|
||||
macctrl |= (np->rx_flow) ?
|
||||
RxFlowControlEnable : 0;
|
||||
writew(macctrl, ioaddr + MACCtrl);
|
||||
dw16(MACCtrl, macctrl);
|
||||
np->link_status = 1;
|
||||
netif_carrier_on(dev);
|
||||
} else {
|
||||
@ -974,7 +968,7 @@ rio_error (struct net_device *dev, int int_status)
|
||||
if (int_status & HostError) {
|
||||
printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
|
||||
dev->name, int_status);
|
||||
writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
|
||||
dw16(ASICCtrl + 2, GlobalReset | HostReset);
|
||||
mdelay (500);
|
||||
}
|
||||
}
|
||||
@ -982,8 +976,8 @@ rio_error (struct net_device *dev, int int_status)
|
||||
static struct net_device_stats *
|
||||
get_stats (struct net_device *dev)
|
||||
{
|
||||
long ioaddr = dev->base_addr;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
#ifdef MEM_MAPPING
|
||||
int i;
|
||||
#endif
|
||||
@ -992,106 +986,107 @@ get_stats (struct net_device *dev)
|
||||
/* All statistics registers need to be acknowledged,
|
||||
else statistic overflow could cause problems */
|
||||
|
||||
np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
|
||||
np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
|
||||
np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
|
||||
np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
|
||||
np->stats.rx_packets += dr32(FramesRcvOk);
|
||||
np->stats.tx_packets += dr32(FramesXmtOk);
|
||||
np->stats.rx_bytes += dr32(OctetRcvOk);
|
||||
np->stats.tx_bytes += dr32(OctetXmtOk);
|
||||
|
||||
np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
|
||||
np->stats.collisions += readl (ioaddr + SingleColFrames)
|
||||
+ readl (ioaddr + MultiColFrames);
|
||||
np->stats.multicast = dr32(McstFramesRcvdOk);
|
||||
np->stats.collisions += dr32(SingleColFrames)
|
||||
+ dr32(MultiColFrames);
|
||||
|
||||
/* detailed tx errors */
|
||||
stat_reg = readw (ioaddr + FramesAbortXSColls);
|
||||
stat_reg = dr16(FramesAbortXSColls);
|
||||
np->stats.tx_aborted_errors += stat_reg;
|
||||
np->stats.tx_errors += stat_reg;
|
||||
|
||||
stat_reg = readw (ioaddr + CarrierSenseErrors);
|
||||
stat_reg = dr16(CarrierSenseErrors);
|
||||
np->stats.tx_carrier_errors += stat_reg;
|
||||
np->stats.tx_errors += stat_reg;
|
||||
|
||||
/* Clear all other statistic register. */
|
||||
readl (ioaddr + McstOctetXmtOk);
|
||||
readw (ioaddr + BcstFramesXmtdOk);
|
||||
readl (ioaddr + McstFramesXmtdOk);
|
||||
readw (ioaddr + BcstFramesRcvdOk);
|
||||
readw (ioaddr + MacControlFramesRcvd);
|
||||
readw (ioaddr + FrameTooLongErrors);
|
||||
readw (ioaddr + InRangeLengthErrors);
|
||||
readw (ioaddr + FramesCheckSeqErrors);
|
||||
readw (ioaddr + FramesLostRxErrors);
|
||||
readl (ioaddr + McstOctetXmtOk);
|
||||
readl (ioaddr + BcstOctetXmtOk);
|
||||
readl (ioaddr + McstFramesXmtdOk);
|
||||
readl (ioaddr + FramesWDeferredXmt);
|
||||
readl (ioaddr + LateCollisions);
|
||||
readw (ioaddr + BcstFramesXmtdOk);
|
||||
readw (ioaddr + MacControlFramesXmtd);
|
||||
readw (ioaddr + FramesWEXDeferal);
|
||||
dr32(McstOctetXmtOk);
|
||||
dr16(BcstFramesXmtdOk);
|
||||
dr32(McstFramesXmtdOk);
|
||||
dr16(BcstFramesRcvdOk);
|
||||
dr16(MacControlFramesRcvd);
|
||||
dr16(FrameTooLongErrors);
|
||||
dr16(InRangeLengthErrors);
|
||||
dr16(FramesCheckSeqErrors);
|
||||
dr16(FramesLostRxErrors);
|
||||
dr32(McstOctetXmtOk);
|
||||
dr32(BcstOctetXmtOk);
|
||||
dr32(McstFramesXmtdOk);
|
||||
dr32(FramesWDeferredXmt);
|
||||
dr32(LateCollisions);
|
||||
dr16(BcstFramesXmtdOk);
|
||||
dr16(MacControlFramesXmtd);
|
||||
dr16(FramesWEXDeferal);
|
||||
|
||||
#ifdef MEM_MAPPING
|
||||
for (i = 0x100; i <= 0x150; i += 4)
|
||||
readl (ioaddr + i);
|
||||
dr32(i);
|
||||
#endif
|
||||
readw (ioaddr + TxJumboFrames);
|
||||
readw (ioaddr + RxJumboFrames);
|
||||
readw (ioaddr + TCPCheckSumErrors);
|
||||
readw (ioaddr + UDPCheckSumErrors);
|
||||
readw (ioaddr + IPCheckSumErrors);
|
||||
dr16(TxJumboFrames);
|
||||
dr16(RxJumboFrames);
|
||||
dr16(TCPCheckSumErrors);
|
||||
dr16(UDPCheckSumErrors);
|
||||
dr16(IPCheckSumErrors);
|
||||
return &np->stats;
|
||||
}
|
||||
|
||||
static int
|
||||
clear_stats (struct net_device *dev)
|
||||
{
|
||||
long ioaddr = dev->base_addr;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
#ifdef MEM_MAPPING
|
||||
int i;
|
||||
#endif
|
||||
|
||||
/* All statistics registers need to be acknowledged,
|
||||
else statistic overflow could cause problems */
|
||||
readl (ioaddr + FramesRcvOk);
|
||||
readl (ioaddr + FramesXmtOk);
|
||||
readl (ioaddr + OctetRcvOk);
|
||||
readl (ioaddr + OctetXmtOk);
|
||||
dr32(FramesRcvOk);
|
||||
dr32(FramesXmtOk);
|
||||
dr32(OctetRcvOk);
|
||||
dr32(OctetXmtOk);
|
||||
|
||||
readl (ioaddr + McstFramesRcvdOk);
|
||||
readl (ioaddr + SingleColFrames);
|
||||
readl (ioaddr + MultiColFrames);
|
||||
readl (ioaddr + LateCollisions);
|
||||
dr32(McstFramesRcvdOk);
|
||||
dr32(SingleColFrames);
|
||||
dr32(MultiColFrames);
|
||||
dr32(LateCollisions);
|
||||
/* detailed rx errors */
|
||||
readw (ioaddr + FrameTooLongErrors);
|
||||
readw (ioaddr + InRangeLengthErrors);
|
||||
readw (ioaddr + FramesCheckSeqErrors);
|
||||
readw (ioaddr + FramesLostRxErrors);
|
||||
dr16(FrameTooLongErrors);
|
||||
dr16(InRangeLengthErrors);
|
||||
dr16(FramesCheckSeqErrors);
|
||||
dr16(FramesLostRxErrors);
|
||||
|
||||
/* detailed tx errors */
|
||||
readw (ioaddr + FramesAbortXSColls);
|
||||
readw (ioaddr + CarrierSenseErrors);
|
||||
dr16(FramesAbortXSColls);
|
||||
dr16(CarrierSenseErrors);
|
||||
|
||||
/* Clear all other statistic register. */
|
||||
readl (ioaddr + McstOctetXmtOk);
|
||||
readw (ioaddr + BcstFramesXmtdOk);
|
||||
readl (ioaddr + McstFramesXmtdOk);
|
||||
readw (ioaddr + BcstFramesRcvdOk);
|
||||
readw (ioaddr + MacControlFramesRcvd);
|
||||
readl (ioaddr + McstOctetXmtOk);
|
||||
readl (ioaddr + BcstOctetXmtOk);
|
||||
readl (ioaddr + McstFramesXmtdOk);
|
||||
readl (ioaddr + FramesWDeferredXmt);
|
||||
readw (ioaddr + BcstFramesXmtdOk);
|
||||
readw (ioaddr + MacControlFramesXmtd);
|
||||
readw (ioaddr + FramesWEXDeferal);
|
||||
dr32(McstOctetXmtOk);
|
||||
dr16(BcstFramesXmtdOk);
|
||||
dr32(McstFramesXmtdOk);
|
||||
dr16(BcstFramesRcvdOk);
|
||||
dr16(MacControlFramesRcvd);
|
||||
dr32(McstOctetXmtOk);
|
||||
dr32(BcstOctetXmtOk);
|
||||
dr32(McstFramesXmtdOk);
|
||||
dr32(FramesWDeferredXmt);
|
||||
dr16(BcstFramesXmtdOk);
|
||||
dr16(MacControlFramesXmtd);
|
||||
dr16(FramesWEXDeferal);
|
||||
#ifdef MEM_MAPPING
|
||||
for (i = 0x100; i <= 0x150; i += 4)
|
||||
readl (ioaddr + i);
|
||||
dr32(i);
|
||||
#endif
|
||||
readw (ioaddr + TxJumboFrames);
|
||||
readw (ioaddr + RxJumboFrames);
|
||||
readw (ioaddr + TCPCheckSumErrors);
|
||||
readw (ioaddr + UDPCheckSumErrors);
|
||||
readw (ioaddr + IPCheckSumErrors);
|
||||
dr16(TxJumboFrames);
|
||||
dr16(RxJumboFrames);
|
||||
dr16(TCPCheckSumErrors);
|
||||
dr16(UDPCheckSumErrors);
|
||||
dr16(IPCheckSumErrors);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1114,10 +1109,10 @@ change_mtu (struct net_device *dev, int new_mtu)
|
||||
static void
|
||||
set_multicast (struct net_device *dev)
|
||||
{
|
||||
long ioaddr = dev->base_addr;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
u32 hash_table[2];
|
||||
u16 rx_mode = 0;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
|
||||
hash_table[0] = hash_table[1] = 0;
|
||||
/* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
|
||||
@ -1153,9 +1148,9 @@ set_multicast (struct net_device *dev)
|
||||
rx_mode |= ReceiveVLANMatch;
|
||||
}
|
||||
|
||||
writel (hash_table[0], ioaddr + HashTable0);
|
||||
writel (hash_table[1], ioaddr + HashTable1);
|
||||
writew (rx_mode, ioaddr + ReceiveMode);
|
||||
dw32(HashTable0, hash_table[0]);
|
||||
dw32(HashTable1, hash_table[1]);
|
||||
dw16(ReceiveMode, rx_mode);
|
||||
}
|
||||
|
||||
static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
|
||||
@ -1318,15 +1313,15 @@ rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
|
||||
#define EEP_BUSY 0x8000
|
||||
/* Read the EEPROM word */
|
||||
/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
|
||||
static int
|
||||
read_eeprom (long ioaddr, int eep_addr)
|
||||
static int read_eeprom(struct netdev_private *np, int eep_addr)
|
||||
{
|
||||
void __iomem *ioaddr = np->eeprom_addr;
|
||||
int i = 1000;
|
||||
outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
|
||||
|
||||
dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
|
||||
while (i-- > 0) {
|
||||
if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
|
||||
return inw (ioaddr + EepromData);
|
||||
}
|
||||
if (!(dr16(EepromCtrl) & EEP_BUSY))
|
||||
return dr16(EepromData);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -1336,38 +1331,40 @@ enum phy_ctrl_bits {
|
||||
MII_DUPLEX = 0x08,
|
||||
};
|
||||
|
||||
#define mii_delay() readb(ioaddr)
|
||||
#define mii_delay() dr8(PhyCtrl)
|
||||
static void
|
||||
mii_sendbit (struct net_device *dev, u32 data)
|
||||
{
|
||||
long ioaddr = dev->base_addr + PhyCtrl;
|
||||
data = (data) ? MII_DATA1 : 0;
|
||||
data |= MII_WRITE;
|
||||
data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
|
||||
writeb (data, ioaddr);
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
|
||||
data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
|
||||
dw8(PhyCtrl, data);
|
||||
mii_delay ();
|
||||
writeb (data | MII_CLK, ioaddr);
|
||||
dw8(PhyCtrl, data | MII_CLK);
|
||||
mii_delay ();
|
||||
}
|
||||
|
||||
static int
|
||||
mii_getbit (struct net_device *dev)
|
||||
{
|
||||
long ioaddr = dev->base_addr + PhyCtrl;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
u8 data;
|
||||
|
||||
data = (readb (ioaddr) & 0xf8) | MII_READ;
|
||||
writeb (data, ioaddr);
|
||||
data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
|
||||
dw8(PhyCtrl, data);
|
||||
mii_delay ();
|
||||
writeb (data | MII_CLK, ioaddr);
|
||||
dw8(PhyCtrl, data | MII_CLK);
|
||||
mii_delay ();
|
||||
return ((readb (ioaddr) >> 1) & 1);
|
||||
return (dr8(PhyCtrl) >> 1) & 1;
|
||||
}
|
||||
|
||||
static void
|
||||
mii_send_bits (struct net_device *dev, u32 data, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = len - 1; i >= 0; i--) {
|
||||
mii_sendbit (dev, data & (1 << i));
|
||||
}
|
||||
@ -1721,28 +1718,29 @@ mii_set_media_pcs (struct net_device *dev)
|
||||
static int
|
||||
rio_close (struct net_device *dev)
|
||||
{
|
||||
long ioaddr = dev->base_addr;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
|
||||
struct pci_dev *pdev = np->pdev;
|
||||
struct sk_buff *skb;
|
||||
int i;
|
||||
|
||||
netif_stop_queue (dev);
|
||||
|
||||
/* Disable interrupts */
|
||||
writew (0, ioaddr + IntEnable);
|
||||
dw16(IntEnable, 0);
|
||||
|
||||
/* Stop Tx and Rx logics */
|
||||
writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
|
||||
dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
|
||||
|
||||
free_irq (dev->irq, dev);
|
||||
free_irq(pdev->irq, dev);
|
||||
del_timer_sync (&np->timer);
|
||||
|
||||
/* Free all the skbuffs in the queue. */
|
||||
for (i = 0; i < RX_RING_SIZE; i++) {
|
||||
skb = np->rx_skbuff[i];
|
||||
if (skb) {
|
||||
pci_unmap_single(np->pdev,
|
||||
desc_to_dma(&np->rx_ring[i]),
|
||||
pci_unmap_single(pdev, desc_to_dma(&np->rx_ring[i]),
|
||||
skb->len, PCI_DMA_FROMDEVICE);
|
||||
dev_kfree_skb (skb);
|
||||
np->rx_skbuff[i] = NULL;
|
||||
@ -1753,8 +1751,7 @@ rio_close (struct net_device *dev)
|
||||
for (i = 0; i < TX_RING_SIZE; i++) {
|
||||
skb = np->tx_skbuff[i];
|
||||
if (skb) {
|
||||
pci_unmap_single(np->pdev,
|
||||
desc_to_dma(&np->tx_ring[i]),
|
||||
pci_unmap_single(pdev, desc_to_dma(&np->tx_ring[i]),
|
||||
skb->len, PCI_DMA_TODEVICE);
|
||||
dev_kfree_skb (skb);
|
||||
np->tx_skbuff[i] = NULL;
|
||||
@ -1778,8 +1775,9 @@ rio_remove1 (struct pci_dev *pdev)
|
||||
pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
|
||||
np->tx_ring_dma);
|
||||
#ifdef MEM_MAPPING
|
||||
iounmap ((char *) (dev->base_addr));
|
||||
pci_iounmap(pdev, np->ioaddr);
|
||||
#endif
|
||||
pci_iounmap(pdev, np->eeprom_addr);
|
||||
free_netdev (dev);
|
||||
pci_release_regions (pdev);
|
||||
pci_disable_device (pdev);
|
||||
|
||||
@ -42,23 +42,6 @@
|
||||
#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
|
||||
#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
|
||||
|
||||
/* This driver was written to use PCI memory space, however x86-oriented
|
||||
hardware often uses I/O space accesses. */
|
||||
#ifndef MEM_MAPPING
|
||||
#undef readb
|
||||
#undef readw
|
||||
#undef readl
|
||||
#undef writeb
|
||||
#undef writew
|
||||
#undef writel
|
||||
#define readb inb
|
||||
#define readw inw
|
||||
#define readl inl
|
||||
#define writeb outb
|
||||
#define writew outw
|
||||
#define writel outl
|
||||
#endif
|
||||
|
||||
/* Offsets to the device registers.
|
||||
Unlike software-only systems, device drivers interact with complex hardware.
|
||||
It's not useful to define symbolic names for every register bit in the
|
||||
@ -391,6 +374,8 @@ struct netdev_private {
|
||||
dma_addr_t tx_ring_dma;
|
||||
dma_addr_t rx_ring_dma;
|
||||
struct pci_dev *pdev;
|
||||
void __iomem *ioaddr;
|
||||
void __iomem *eeprom_addr;
|
||||
spinlock_t tx_lock;
|
||||
spinlock_t rx_lock;
|
||||
struct net_device_stats stats;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user