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IOMMU Fixes for Linux v5.5-rc7
Two Fixes: - Fix NULL-ptr dereference bug in Intel IOMMU driver - Properly safe and restore AMD IOMMU performance counter registers when testing if they are writable. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAl4rKJ0ACgkQK/BELZcB GuM8BxAAse7i4EAB0DZ26aDVU/ZZAGBTc5pH+7IOvuGFWpu3Ik7siltMZKTa56XD 5reQl1hUHyBesdwNcd+ZQz/0QzgMu0zEcxJtzLD5nbk2Rp1pDYab84+wA0oqftmN 7TBqPJjqGYfnfkobPW+4SaiCSxM6XKEXYaJvXqF6dsz5fLHHqTVjGyEXuu0pWey5 1AG1nNWey5TobR39ZUNVIGUEf4ftN8tOGutjGKch29OmMg1UkHZjDyYpVJurjSUl 1YDf0WA2X5cUWzRg519o9Uxs+5y/tBItS2qMJ/Uwh1fp/kOYrGoEPXRH9brU3owh j8kVKyz/cNlvhdJN/QPVq/A+GBgzAq+u9FUGH68LBVx05cuCRGWb6qP/blEZWUSA zQvbHPIPqPBK0pYtbVCgJFCpOS5C6X33RMgbRr3XncAItmfEp2FH7tcHIsDZUzmO EGBgSPrhRFJrgfa3hopc93L4OEHmGy+20o7oT4kk0SBcHVDSyDZVBu1lX+/gAZKd ZoV5FyF9KNB+qQQ6E+vpL5gLh7BWiBgOI41Bdw5ut09I0gYURPdFWUPHRFwHK1/1 KTSWLyuLkS4VxdhcwhA30eVmSrbfocPPwuUxcGn2p1YnaycFkDNoJnhifvFiOS6w tFOJ3wEVL2OX7On6U3jviVy7MQapX3MvWrWKlgg/UoMv36dbqRA= =ViDp -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v5.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: "Two fixes: - Fix NULL-ptr dereference bug in Intel IOMMU driver - Properly save and restore AMD IOMMU performance counter registers when testing if they are writable" * tag 'iommu-fixes-v5.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/amd: Fix IOMMU perf counter clobbering during init iommu/vt-d: Call __dmar_remove_one_dev_info with valid pointer
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commit
6381b44283
@ -1655,27 +1655,39 @@ static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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static void init_iommu_perf_ctr(struct amd_iommu *iommu)
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{
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struct pci_dev *pdev = iommu->dev;
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u64 val = 0xabcd, val2 = 0;
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u64 val = 0xabcd, val2 = 0, save_reg = 0;
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if (!iommu_feature(iommu, FEATURE_PC))
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return;
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amd_iommu_pc_present = true;
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/* save the value to restore, if writable */
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if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false))
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goto pc_false;
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/* Check if the performance counters can be written to */
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if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
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(iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
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(val != val2)) {
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pci_err(pdev, "Unable to write to IOMMU perf counter.\n");
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amd_iommu_pc_present = false;
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return;
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}
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(val != val2))
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goto pc_false;
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/* restore */
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if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true))
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goto pc_false;
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pci_info(pdev, "IOMMU performance counters supported\n");
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val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
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iommu->max_banks = (u8) ((val >> 12) & 0x3f);
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iommu->max_counters = (u8) ((val >> 7) & 0xf);
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return;
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pc_false:
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pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n");
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amd_iommu_pc_present = false;
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return;
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}
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static ssize_t amd_iommu_show_cap(struct device *dev,
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@ -5163,7 +5163,8 @@ static void dmar_remove_one_dev_info(struct device *dev)
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spin_lock_irqsave(&device_domain_lock, flags);
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info = dev->archdata.iommu;
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if (info)
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if (info && info != DEFER_DEVICE_DOMAIN_INFO
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&& info != DUMMY_DEVICE_DOMAIN_INFO)
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__dmar_remove_one_dev_info(info);
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spin_unlock_irqrestore(&device_domain_lock, flags);
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}
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