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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-12-29 17:25:38 +00:00
KVM: arm64: Rip out the vestiges of the 'old' ID register scheme
There's no longer a need for the baggage of the old scheme for handling configurable ID register fields. Rip it all out in favor of the generalized infrastructure. Link: https://lore.kernel.org/r/20230609190054.1542113-12-oliver.upton@linux.dev Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Oliver Upton
parent
6db7af0d5b
commit
686672407e
@ -241,10 +241,6 @@ struct kvm_arch {
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cpumask_var_t supported_cpus;
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u8 pfr0_csv2;
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u8 pfr0_csv3;
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u8 dfr0_pmuver;
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/* Hypercall features firmware registers' descriptor */
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struct kvm_smccc_features smccc_feat;
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struct maple_tree smccc_filter;
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@ -102,22 +102,6 @@ static int kvm_arm_default_max_vcpus(void)
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return vgic_present ? kvm_vgic_get_max_vcpus() : KVM_MAX_VCPUS;
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}
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static void set_default_spectre(struct kvm *kvm)
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{
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/*
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* The default is to expose CSV2 == 1 if the HW isn't affected.
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* Although this is a per-CPU feature, we make it global because
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* asymmetric systems are just a nuisance.
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*
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* Userspace can override this as long as it doesn't promise
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* the impossible.
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*/
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if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
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kvm->arch.pfr0_csv2 = 1;
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if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED)
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kvm->arch.pfr0_csv3 = 1;
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}
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/**
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* kvm_arch_init_vm - initializes a VM data structure
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* @kvm: pointer to the KVM struct
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@ -161,15 +145,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
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/* The maximum number of VCPUs is limited by the host's GIC model */
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kvm->max_vcpus = kvm_arm_default_max_vcpus();
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set_default_spectre(kvm);
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kvm_arm_init_hypercalls(kvm);
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/*
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* Initialise the default PMUver before there is a chance to
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* create an actual PMU.
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*/
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kvm->arch.dfr0_pmuver = kvm_arm_pmu_get_pmuver_limit();
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bitmap_zero(kvm->arch.vcpu_features, KVM_VCPU_MAX_FEATURES);
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return 0;
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@ -1195,14 +1195,6 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
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return true;
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}
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static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
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{
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if (kvm_vcpu_has_pmu(vcpu))
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return vcpu->kvm->arch.dfr0_pmuver;
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return 0;
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}
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static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
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s64 new, s64 cur)
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{
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@ -1288,19 +1280,6 @@ static int arm64_check_features(struct kvm_vcpu *vcpu,
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return 0;
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}
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static u8 perfmon_to_pmuver(u8 perfmon)
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{
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switch (perfmon) {
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case ID_DFR0_EL1_PerfMon_PMUv3:
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return ID_AA64DFR0_EL1_PMUVer_IMP;
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case ID_DFR0_EL1_PerfMon_IMPDEF:
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return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
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default:
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/* Anything ARMv8.1+ and NI have the same value. For now. */
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return perfmon;
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}
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}
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static u8 pmuver_to_perfmon(u8 pmuver)
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{
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switch (pmuver) {
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@ -1327,19 +1306,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
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val = read_sanitised_ftr_reg(id);
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switch (id) {
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case SYS_ID_AA64PFR0_EL1:
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if (!vcpu_has_sve(vcpu))
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
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if (kvm_vgic_global_state.type == VGIC_V3) {
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
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}
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break;
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case SYS_ID_AA64PFR1_EL1:
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if (!kvm_has_mte(vcpu->kvm))
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val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
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@ -1360,22 +1326,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
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if (!cpus_have_final_cap(ARM64_HAS_WFXT))
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val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
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break;
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case SYS_ID_AA64DFR0_EL1:
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/* Limit debug to ARMv8.0 */
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
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/* Set PMUver to the required version */
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
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vcpu_pmuver(vcpu));
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/* Hide SPE from guests */
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
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break;
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case SYS_ID_DFR0_EL1:
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val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon),
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pmuver_to_perfmon(vcpu_pmuver(vcpu)));
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break;
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case SYS_ID_AA64MMFR2_EL1:
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val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
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break;
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@ -1505,26 +1455,6 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
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return val;
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}
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static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd,
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u64 val)
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{
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u8 csv2, csv3;
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int r;
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csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT);
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csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT);
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r = set_id_reg(vcpu, rd, val);
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if (r)
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return r;
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vcpu->kvm->arch.pfr0_csv2 = csv2;
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vcpu->kvm->arch.pfr0_csv3 = csv3;
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return 0;
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}
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static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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@ -1553,7 +1483,6 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
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u64 val)
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{
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u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
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int r;
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/*
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* Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
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@ -1569,17 +1498,10 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
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* surprising than an ill-guided PMU driver poking at impdef system
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* registers that end in an UNDEF...
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*/
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if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) {
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if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
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val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
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pmuver = 0;
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}
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r = set_id_reg(vcpu, rd, val);
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if (r)
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return r;
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vcpu->kvm->arch.dfr0_pmuver = pmuver;
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return 0;
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return set_id_reg(vcpu, rd, val);
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}
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static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
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@ -1600,7 +1522,6 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
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u64 val)
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{
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u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
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int r;
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if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
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val &= ~ID_DFR0_EL1_PerfMon_MASK;
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@ -1616,12 +1537,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
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if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
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return -EINVAL;
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r = set_id_reg(vcpu, rd, val);
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if (r)
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return r;
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vcpu->kvm->arch.dfr0_pmuver = perfmon_to_pmuver(perfmon);
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return 0;
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return set_id_reg(vcpu, rd, val);
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}
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/*
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@ -2076,7 +1992,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_ID_AA64PFR0_EL1),
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.access = access_id_reg,
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.get_user = get_id_reg,
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.set_user = set_id_aa64pfr0_el1,
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.set_user = set_id_reg,
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.reset = read_sanitised_id_aa64pfr0_el1,
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.val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
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ID_SANITISED(ID_AA64PFR1_EL1),
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@ -92,8 +92,12 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
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/*
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* Evaluates as true when emulating PMUv3p5, and false otherwise.
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*/
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#define kvm_pmu_is_3p5(vcpu) \
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(vcpu->kvm->arch.dfr0_pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5)
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#define kvm_pmu_is_3p5(vcpu) ({ \
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u64 val = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); \
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u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); \
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\
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pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5; \
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})
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u8 kvm_arm_pmu_get_pmuver_limit(void);
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