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NAND controller fix:
* gpmi: Fix busy timeout setting (wrong calculation, yes again) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdgfidid8lnn52cLTZvlZhesYu8EFAmLZZ/AACgkQZvlZhesY u8F79A//QHt/NthTJBA9cn2ahrW0ToZyIIPhrRvUYzUWrfddxDOWjRSZ0ElFGcfz krHuAlopLrZFOI5/Qrp5DQ+skeII0l9KnKZ3xmSvbAVflqtyACXkR8e630AkYFjE v6eBEdll4saBy58oCaZTGvM4jjJH+kzfUnUJIRWXBV46FBN0f/2Qn2T1SJbZRb// kpgwF94jNgd2ExH3ZgosFxzkUIwvO3/JHm7R1FCZyfUfrKip+1eLTAJ2x1HfNNSH +SkzESpD7GRLzuaeV+S5xIuYrLLuw7lmlZSSvhZN/KyNYFYHVKviDc3q91QZ5+lO Gtu7uj8ZqU3600OeauMR34pLiVd+6wU4tQljSFH874UXNRsd8e/obUpa5YrS7wd1 tu8mkd4bymIylgVn8l+pNRYnjv8FPzBdX/T2b2zQmd5F4XlhjjST78uA96UmN6I5 XD27mH+mcL7JCyiJkqeUvRP8Hy9ja+JAqR6AxLF6GnsntbySo9Hy2mAiqkdJMrbP QfSDhWRi2AIrQOuxgSU5LcGPyBedomWHiRRn3cxIc1pQWBtrJj0YeKq5Vv0yfWnn TLiRkDgzp8DYDvtcqKVQmYcPcD8hSgItS145jbJE/h2/3VguXjYCSNczOKWBgdT1 fNTDXWgnjxRoq155gB/VPtpmXbZmF4zN8qojHMZt+xRMlLZph5s= =sVYq -----END PGP SIGNATURE----- Merge tag 'mtd/fixes-for-5.19-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD fix from Richard Weinberger: "A aingle NAND controller fix: - gpmi: Fix busy timeout setting (wrong calculation, yes again)" * tag 'mtd/fixes-for-5.19-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: rawnand: gpmi: Set WAIT_FOR_READY timeout based on program/erase times
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commit
68e77ffbfd
@ -850,9 +850,10 @@ static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
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unsigned int tRP_ps;
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bool use_half_period;
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int sample_delay_ps, sample_delay_factor;
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u16 busy_timeout_cycles;
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unsigned int busy_timeout_cycles;
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u8 wrn_dly_sel;
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unsigned long clk_rate, min_rate;
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u64 busy_timeout_ps;
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if (sdr->tRC_min >= 30000) {
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/* ONFI non-EDO modes [0-3] */
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@ -885,7 +886,8 @@ static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
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addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps);
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data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps);
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data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps);
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busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
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busy_timeout_ps = max(sdr->tBERS_max, sdr->tPROG_max);
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busy_timeout_cycles = TO_CYCLES(busy_timeout_ps, period_ps);
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hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) |
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BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) |
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