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drivers/perf: hisi: Add Support for CPA PMU
On HiSilicon Hip09 platform, there is a CPA (Coherency Protocol Agent) on each SICL (Super IO Cluster) which implements packet format translation, route parsing and traffic statistics. CPA PMU has 8 PMU counters and interrupt is supported to handle counter overflow. Let's support its driver under the framework of HiSilicon PMU driver. Signed-off-by: Qi Liu <liuqi115@huawei.com> Reviewed-by: John Garry <john.garry@huawei.com> Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Link: https://lore.kernel.org/r/20220415102352.6665-3-liuqi115@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Qi Liu
Will Deacon
parent
807907dae9
commit
6b79738b6e
@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o \
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hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o hisi_uncore_sllc_pmu.o \
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hisi_uncore_pa_pmu.o
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hisi_uncore_pa_pmu.o hisi_uncore_cpa_pmu.o
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obj-$(CONFIG_HISI_PCIE_PMU) += hisi_pcie_pmu.o
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409
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
Normal file
409
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
Normal file
@ -0,0 +1,409 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HiSilicon SoC CPA(Coherency Protocol Agent) hardware event counters support
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*
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* Copyright (C) 2022 HiSilicon Limited
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* Author: Qi Liu <liuqi115@huawei.com>
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*
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* This code is based on the uncore PMUs like arm-cci and arm-ccn.
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*/
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#define pr_fmt(fmt) "cpa pmu: " fmt
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#include <linux/acpi.h>
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#include <linux/bug.h>
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#include <linux/cpuhotplug.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include "hisi_uncore_pmu.h"
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/* CPA register definition */
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#define CPA_PERF_CTRL 0x1c00
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#define CPA_EVENT_CTRL 0x1c04
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#define CPA_INT_MASK 0x1c70
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#define CPA_INT_STATUS 0x1c78
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#define CPA_INT_CLEAR 0x1c7c
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#define CPA_EVENT_TYPE0 0x1c80
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#define CPA_VERSION 0x1cf0
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#define CPA_CNT0_LOWER 0x1d00
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#define CPA_CFG_REG 0x0534
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/* CPA operation command */
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#define CPA_PERF_CTRL_EN BIT_ULL(0)
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#define CPA_EVTYPE_MASK 0xffUL
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#define CPA_PM_CTRL BIT_ULL(9)
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/* CPA has 8-counters */
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#define CPA_NR_COUNTERS 0x8
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#define CPA_COUNTER_BITS 64
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#define CPA_NR_EVENTS 0xff
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#define CPA_REG_OFFSET 0x8
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static u32 hisi_cpa_pmu_get_counter_offset(int idx)
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{
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return (CPA_CNT0_LOWER + idx * CPA_REG_OFFSET);
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}
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static u64 hisi_cpa_pmu_read_counter(struct hisi_pmu *cpa_pmu,
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struct hw_perf_event *hwc)
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{
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return readq(cpa_pmu->base + hisi_cpa_pmu_get_counter_offset(hwc->idx));
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}
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static void hisi_cpa_pmu_write_counter(struct hisi_pmu *cpa_pmu,
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struct hw_perf_event *hwc, u64 val)
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{
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writeq(val, cpa_pmu->base + hisi_cpa_pmu_get_counter_offset(hwc->idx));
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}
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static void hisi_cpa_pmu_write_evtype(struct hisi_pmu *cpa_pmu, int idx,
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u32 type)
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{
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u32 reg, reg_idx, shift, val;
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/*
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* Select the appropriate event select register(CPA_EVENT_TYPE0/1).
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* There are 2 event select registers for the 8 hardware counters.
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* Event code is 8-bits and for the former 4 hardware counters,
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* CPA_EVENT_TYPE0 is chosen. For the latter 4 hardware counters,
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* CPA_EVENT_TYPE1 is chosen.
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*/
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reg = CPA_EVENT_TYPE0 + (idx / 4) * 4;
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reg_idx = idx % 4;
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shift = CPA_REG_OFFSET * reg_idx;
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/* Write event code to CPA_EVENT_TYPEx Register */
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val = readl(cpa_pmu->base + reg);
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val &= ~(CPA_EVTYPE_MASK << shift);
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val |= type << shift;
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writel(val, cpa_pmu->base + reg);
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}
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static void hisi_cpa_pmu_start_counters(struct hisi_pmu *cpa_pmu)
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{
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u32 val;
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val = readl(cpa_pmu->base + CPA_PERF_CTRL);
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val |= CPA_PERF_CTRL_EN;
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writel(val, cpa_pmu->base + CPA_PERF_CTRL);
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}
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static void hisi_cpa_pmu_stop_counters(struct hisi_pmu *cpa_pmu)
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{
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u32 val;
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val = readl(cpa_pmu->base + CPA_PERF_CTRL);
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val &= ~(CPA_PERF_CTRL_EN);
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writel(val, cpa_pmu->base + CPA_PERF_CTRL);
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}
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static void hisi_cpa_pmu_disable_pm(struct hisi_pmu *cpa_pmu)
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{
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u32 val;
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val = readl(cpa_pmu->base + CPA_CFG_REG);
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val |= CPA_PM_CTRL;
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writel(val, cpa_pmu->base + CPA_CFG_REG);
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}
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static void hisi_cpa_pmu_enable_pm(struct hisi_pmu *cpa_pmu)
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{
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u32 val;
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val = readl(cpa_pmu->base + CPA_CFG_REG);
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val &= ~(CPA_PM_CTRL);
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writel(val, cpa_pmu->base + CPA_CFG_REG);
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}
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static void hisi_cpa_pmu_enable_counter(struct hisi_pmu *cpa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Enable counter index in CPA_EVENT_CTRL register */
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val = readl(cpa_pmu->base + CPA_EVENT_CTRL);
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val |= 1 << hwc->idx;
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writel(val, cpa_pmu->base + CPA_EVENT_CTRL);
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}
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static void hisi_cpa_pmu_disable_counter(struct hisi_pmu *cpa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Clear counter index in CPA_EVENT_CTRL register */
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val = readl(cpa_pmu->base + CPA_EVENT_CTRL);
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val &= ~(1UL << hwc->idx);
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writel(val, cpa_pmu->base + CPA_EVENT_CTRL);
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}
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static void hisi_cpa_pmu_enable_counter_int(struct hisi_pmu *cpa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 0 to enable interrupt */
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val = readl(cpa_pmu->base + CPA_INT_MASK);
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val &= ~(1UL << hwc->idx);
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writel(val, cpa_pmu->base + CPA_INT_MASK);
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}
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static void hisi_cpa_pmu_disable_counter_int(struct hisi_pmu *cpa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 1 to mask interrupt */
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val = readl(cpa_pmu->base + CPA_INT_MASK);
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val |= 1 << hwc->idx;
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writel(val, cpa_pmu->base + CPA_INT_MASK);
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}
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static u32 hisi_cpa_pmu_get_int_status(struct hisi_pmu *cpa_pmu)
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{
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return readl(cpa_pmu->base + CPA_INT_STATUS);
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}
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static void hisi_cpa_pmu_clear_int_status(struct hisi_pmu *cpa_pmu, int idx)
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{
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writel(1 << idx, cpa_pmu->base + CPA_INT_CLEAR);
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}
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static const struct acpi_device_id hisi_cpa_pmu_acpi_match[] = {
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{ "HISI0281", },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, hisi_cpa_pmu_acpi_match);
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static int hisi_cpa_pmu_init_data(struct platform_device *pdev,
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struct hisi_pmu *cpa_pmu)
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{
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if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
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&cpa_pmu->sicl_id)) {
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dev_err(&pdev->dev, "Can not read sicl-id\n");
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return -EINVAL;
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}
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if (device_property_read_u32(&pdev->dev, "hisilicon,idx-id",
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&cpa_pmu->index_id)) {
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dev_err(&pdev->dev, "Cannot read idx-id\n");
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return -EINVAL;
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}
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cpa_pmu->ccl_id = -1;
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cpa_pmu->sccl_id = -1;
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cpa_pmu->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(cpa_pmu->base))
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return PTR_ERR(cpa_pmu->base);
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cpa_pmu->identifier = readl(cpa_pmu->base + CPA_VERSION);
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return 0;
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}
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static struct attribute *hisi_cpa_pmu_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-15"),
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NULL
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};
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static const struct attribute_group hisi_cpa_pmu_format_group = {
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.name = "format",
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.attrs = hisi_cpa_pmu_format_attr,
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};
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static struct attribute *hisi_cpa_pmu_events_attr[] = {
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HISI_PMU_EVENT_ATTR(cpa_cycles, 0x00),
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HISI_PMU_EVENT_ATTR(cpa_p1_wr_dat, 0x61),
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HISI_PMU_EVENT_ATTR(cpa_p1_rd_dat, 0x62),
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HISI_PMU_EVENT_ATTR(cpa_p0_wr_dat, 0xE1),
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HISI_PMU_EVENT_ATTR(cpa_p0_rd_dat, 0xE2),
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NULL
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};
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static const struct attribute_group hisi_cpa_pmu_events_group = {
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.name = "events",
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.attrs = hisi_cpa_pmu_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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static struct attribute *hisi_cpa_pmu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL
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};
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static const struct attribute_group hisi_cpa_pmu_cpumask_attr_group = {
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.attrs = hisi_cpa_pmu_cpumask_attrs,
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};
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static struct device_attribute hisi_cpa_pmu_identifier_attr =
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__ATTR(identifier, 0444, hisi_uncore_pmu_identifier_attr_show, NULL);
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static struct attribute *hisi_cpa_pmu_identifier_attrs[] = {
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&hisi_cpa_pmu_identifier_attr.attr,
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NULL
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};
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static const struct attribute_group hisi_cpa_pmu_identifier_group = {
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.attrs = hisi_cpa_pmu_identifier_attrs,
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};
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static const struct attribute_group *hisi_cpa_pmu_attr_groups[] = {
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&hisi_cpa_pmu_format_group,
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&hisi_cpa_pmu_events_group,
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&hisi_cpa_pmu_cpumask_attr_group,
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&hisi_cpa_pmu_identifier_group,
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NULL
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};
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static const struct hisi_uncore_ops hisi_uncore_cpa_pmu_ops = {
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.write_evtype = hisi_cpa_pmu_write_evtype,
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.get_event_idx = hisi_uncore_pmu_get_event_idx,
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.start_counters = hisi_cpa_pmu_start_counters,
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.stop_counters = hisi_cpa_pmu_stop_counters,
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.enable_counter = hisi_cpa_pmu_enable_counter,
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.disable_counter = hisi_cpa_pmu_disable_counter,
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.enable_counter_int = hisi_cpa_pmu_enable_counter_int,
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.disable_counter_int = hisi_cpa_pmu_disable_counter_int,
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.write_counter = hisi_cpa_pmu_write_counter,
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.read_counter = hisi_cpa_pmu_read_counter,
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.get_int_status = hisi_cpa_pmu_get_int_status,
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.clear_int_status = hisi_cpa_pmu_clear_int_status,
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};
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static int hisi_cpa_pmu_dev_probe(struct platform_device *pdev,
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struct hisi_pmu *cpa_pmu)
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{
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int ret;
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ret = hisi_cpa_pmu_init_data(pdev, cpa_pmu);
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if (ret)
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return ret;
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ret = hisi_uncore_pmu_init_irq(cpa_pmu, pdev);
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if (ret)
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return ret;
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cpa_pmu->counter_bits = CPA_COUNTER_BITS;
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cpa_pmu->check_event = CPA_NR_EVENTS;
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cpa_pmu->pmu_events.attr_groups = hisi_cpa_pmu_attr_groups;
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cpa_pmu->ops = &hisi_uncore_cpa_pmu_ops;
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cpa_pmu->num_counters = CPA_NR_COUNTERS;
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cpa_pmu->dev = &pdev->dev;
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cpa_pmu->on_cpu = -1;
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return 0;
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}
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static int hisi_cpa_pmu_probe(struct platform_device *pdev)
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{
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struct hisi_pmu *cpa_pmu;
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char *name;
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int ret;
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cpa_pmu = devm_kzalloc(&pdev->dev, sizeof(*cpa_pmu), GFP_KERNEL);
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if (!cpa_pmu)
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return -ENOMEM;
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ret = hisi_cpa_pmu_dev_probe(pdev, cpa_pmu);
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if (ret)
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return ret;
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name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sicl%d_cpa%u",
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cpa_pmu->sicl_id, cpa_pmu->index_id);
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if (!name)
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return -ENOMEM;
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cpa_pmu->pmu = (struct pmu) {
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.name = name,
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.module = THIS_MODULE,
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.task_ctx_nr = perf_invalid_context,
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.event_init = hisi_uncore_pmu_event_init,
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.pmu_enable = hisi_uncore_pmu_enable,
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.pmu_disable = hisi_uncore_pmu_disable,
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.add = hisi_uncore_pmu_add,
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.del = hisi_uncore_pmu_del,
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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.attr_groups = cpa_pmu->pmu_events.attr_groups,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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};
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/* Power Management should be disabled before using CPA PMU. */
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hisi_cpa_pmu_disable_pm(cpa_pmu);
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ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE,
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&cpa_pmu->node);
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if (ret) {
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dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
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hisi_cpa_pmu_enable_pm(cpa_pmu);
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return ret;
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}
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ret = perf_pmu_register(&cpa_pmu->pmu, name, -1);
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if (ret) {
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dev_err(cpa_pmu->dev, "PMU register failed\n");
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cpuhp_state_remove_instance_nocalls(
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CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE, &cpa_pmu->node);
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hisi_cpa_pmu_enable_pm(cpa_pmu);
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return ret;
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}
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platform_set_drvdata(pdev, cpa_pmu);
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return ret;
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}
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static int hisi_cpa_pmu_remove(struct platform_device *pdev)
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{
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struct hisi_pmu *cpa_pmu = platform_get_drvdata(pdev);
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perf_pmu_unregister(&cpa_pmu->pmu);
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cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE,
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&cpa_pmu->node);
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hisi_cpa_pmu_enable_pm(cpa_pmu);
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return 0;
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}
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static struct platform_driver hisi_cpa_pmu_driver = {
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.driver = {
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.name = "hisi_cpa_pmu",
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.acpi_match_table = ACPI_PTR(hisi_cpa_pmu_acpi_match),
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.suppress_bind_attrs = true,
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},
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.probe = hisi_cpa_pmu_probe,
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.remove = hisi_cpa_pmu_remove,
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};
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static int __init hisi_cpa_pmu_module_init(void)
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{
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int ret;
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ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE,
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"AP_PERF_ARM_HISI_CPA_ONLINE",
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hisi_uncore_pmu_online_cpu,
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hisi_uncore_pmu_offline_cpu);
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if (ret) {
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pr_err("setup hotplug failed: %d\n", ret);
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return ret;
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}
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ret = platform_driver_register(&hisi_cpa_pmu_driver);
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if (ret)
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cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
module_init(hisi_cpa_pmu_module_init);
|
||||
|
||||
static void __exit hisi_cpa_pmu_module_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&hisi_cpa_pmu_driver);
|
||||
cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE);
|
||||
}
|
||||
module_exit(hisi_cpa_pmu_module_exit);
|
||||
|
||||
MODULE_DESCRIPTION("HiSilicon SoC CPA PMU driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Qi Liu <liuqi115@huawei.com>");
|
||||
@ -222,6 +222,7 @@ enum cpuhp_state {
|
||||
CPUHP_AP_PERF_S390_SF_ONLINE,
|
||||
CPUHP_AP_PERF_ARM_CCI_ONLINE,
|
||||
CPUHP_AP_PERF_ARM_CCN_ONLINE,
|
||||
CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE,
|
||||
CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
|
||||
CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
|
||||
CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user