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irqchip/apple-aic: Add support for AICv2
Introduce support for the new AICv2 hardware block in t6000/t6001 SoCs. It seems these blocks are missing the information required to compute the event register offset in the capability registers, so we specify that in the DT as a second reg entry. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-8-marcan@marcan.st
This commit is contained in:
Hector Martin
Marc Zyngier
parent
a801f0ee56
commit
768d4435de
@ -103,6 +103,58 @@
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#define AIC_MAX_IRQ 0x400
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/*
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* AIC v2 registers (MMIO)
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*/
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#define AIC2_VERSION 0x0000
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#define AIC2_VERSION_VER GENMASK(7, 0)
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#define AIC2_INFO1 0x0004
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#define AIC2_INFO1_NR_IRQ GENMASK(15, 0)
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#define AIC2_INFO1_LAST_DIE GENMASK(27, 24)
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#define AIC2_INFO2 0x0008
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#define AIC2_INFO3 0x000c
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#define AIC2_INFO3_MAX_IRQ GENMASK(15, 0)
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#define AIC2_INFO3_MAX_DIE GENMASK(27, 24)
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#define AIC2_RESET 0x0010
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#define AIC2_RESET_RESET BIT(0)
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#define AIC2_CONFIG 0x0014
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#define AIC2_CONFIG_ENABLE BIT(0)
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#define AIC2_CONFIG_PREFER_PCPU BIT(28)
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#define AIC2_TIMEOUT 0x0028
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#define AIC2_CLUSTER_PRIO 0x0030
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#define AIC2_DELAY_GROUPS 0x0100
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#define AIC2_IRQ_CFG 0x2000
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/*
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* AIC2 registers are laid out like this, starting at AIC2_IRQ_CFG:
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*
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* Repeat for each die:
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* IRQ_CFG: u32 * MAX_IRQS
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* SW_SET: u32 * (MAX_IRQS / 32)
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* SW_CLR: u32 * (MAX_IRQS / 32)
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* MASK_SET: u32 * (MAX_IRQS / 32)
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* MASK_CLR: u32 * (MAX_IRQS / 32)
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* HW_STATE: u32 * (MAX_IRQS / 32)
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*
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* This is followed by a set of event registers, each 16K page aligned.
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* The first one is the AP event register we will use. Unfortunately,
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* the actual implemented die count is not specified anywhere in the
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* capability registers, so we have to explicitly specify the event
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* register as a second reg entry in the device tree to remain
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* forward-compatible.
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*/
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#define AIC2_IRQ_CFG_TARGET GENMASK(3, 0)
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#define AIC2_IRQ_CFG_DELAY_IDX GENMASK(7, 5)
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#define MASK_REG(x) (4 * ((x) >> 5))
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#define MASK_BIT(x) BIT((x) & GENMASK(4, 0))
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@ -193,6 +245,7 @@ struct aic_info {
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/* Register offsets */
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u32 event;
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u32 target_cpu;
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u32 irq_cfg;
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u32 sw_set;
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u32 sw_clr;
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u32 mask_set;
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@ -220,6 +273,14 @@ static const struct aic_info aic1_fipi_info = {
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.fast_ipi = true,
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};
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static const struct aic_info aic2_info = {
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.version = 2,
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.irq_cfg = AIC2_IRQ_CFG,
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.fast_ipi = true,
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};
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static const struct of_device_id aic_info_match[] = {
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{
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.compatible = "apple,t8103-aic",
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@ -229,11 +290,16 @@ static const struct of_device_id aic_info_match[] = {
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.compatible = "apple,aic",
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.data = &aic1_info,
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},
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{
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.compatible = "apple,aic2",
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.data = &aic2_info,
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},
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{}
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};
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struct aic_irq_chip {
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void __iomem *base;
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void __iomem *event;
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struct irq_domain *hw_domain;
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struct irq_domain *ipi_domain;
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@ -310,7 +376,7 @@ static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)
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* We cannot use a relaxed read here, as reads from DMA buffers
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* need to be ordered after the IRQ fires.
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*/
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event = readl(ic->base + ic->info.event);
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event = readl(ic->event + ic->info.event);
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type = FIELD_GET(AIC_EVENT_TYPE, event);
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irq = FIELD_GET(AIC_EVENT_NUM, event);
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@ -373,6 +439,14 @@ static struct irq_chip aic_chip = {
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.irq_set_type = aic_irq_set_type,
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};
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static struct irq_chip aic2_chip = {
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.name = "AIC2",
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.irq_mask = aic_irq_mask,
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.irq_unmask = aic_irq_unmask,
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.irq_eoi = aic_irq_eoi,
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.irq_set_type = aic_irq_set_type,
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};
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/*
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* FIQ irqchip
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*/
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@ -529,10 +603,15 @@ static struct irq_chip fiq_chip = {
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static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct aic_irq_chip *ic = id->host_data;
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u32 type = FIELD_GET(AIC_EVENT_TYPE, hw);
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struct irq_chip *chip = &aic_chip;
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if (ic->info.version == 2)
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chip = &aic2_chip;
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if (type == AIC_EVENT_TYPE_IRQ) {
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irq_domain_set_info(id, irq, hw, &aic_chip, id->host_data,
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irq_domain_set_info(id, irq, hw, chip, id->host_data,
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handle_fasteoi_irq, NULL, NULL);
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
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} else {
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@ -888,24 +967,26 @@ static int aic_init_cpu(unsigned int cpu)
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/* Commit all of the above */
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isb();
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/*
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* Make sure the kernel's idea of logical CPU order is the same as AIC's
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* If we ever end up with a mismatch here, we will have to introduce
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* a mapping table similar to what other irqchip drivers do.
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*/
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WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id());
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if (aic_irqc->info.version == 1) {
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/*
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* Make sure the kernel's idea of logical CPU order is the same as AIC's
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* If we ever end up with a mismatch here, we will have to introduce
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* a mapping table similar to what other irqchip drivers do.
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*/
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WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id());
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/*
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* Always keep IPIs unmasked at the hardware level (except auto-masking
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* by AIC during processing). We manage masks at the vIPI level.
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* These registers only exist on AICv1, AICv2 always uses fast IPIs.
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*/
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aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_SELF | AIC_IPI_OTHER);
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if (static_branch_likely(&use_fast_ipi)) {
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aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER);
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} else {
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aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF);
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aic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER);
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/*
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* Always keep IPIs unmasked at the hardware level (except auto-masking
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* by AIC during processing). We manage masks at the vIPI level.
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* These registers only exist on AICv1, AICv2 always uses fast IPIs.
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*/
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aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_SELF | AIC_IPI_OTHER);
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if (static_branch_likely(&use_fast_ipi)) {
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aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER);
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} else {
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aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF);
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aic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER);
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}
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}
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/* Initialize the local mask state */
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@ -933,14 +1014,16 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
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return -EIO;
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irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
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if (!irqc)
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if (!irqc) {
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iounmap(regs);
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return -ENOMEM;
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}
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irqc->base = regs;
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match = of_match_node(aic_info_match, node);
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if (!match)
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return -ENODEV;
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goto err_unmap;
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irqc->info = *(struct aic_info *)match->data;
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@ -958,6 +1041,28 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
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off = start_off = irqc->info.target_cpu;
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off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */
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irqc->event = irqc->base;
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break;
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}
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case 2: {
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u32 info1, info3;
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info1 = aic_ic_read(irqc, AIC2_INFO1);
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info3 = aic_ic_read(irqc, AIC2_INFO3);
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irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1);
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irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3);
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irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1;
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irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3);
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off = start_off = irqc->info.irq_cfg;
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off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */
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irqc->event = of_iomap(node, 1);
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if (WARN_ON(!irqc->event))
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goto err_unmap;
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break;
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}
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}
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@ -981,20 +1086,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
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irqc->hw_domain = irq_domain_create_tree(of_node_to_fwnode(node),
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&aic_irq_domain_ops, irqc);
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if (WARN_ON(!irqc->hw_domain)) {
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iounmap(irqc->base);
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kfree(irqc);
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return -ENODEV;
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}
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if (WARN_ON(!irqc->hw_domain))
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goto err_unmap;
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irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED);
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if (aic_init_smp(irqc, node)) {
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irq_domain_remove(irqc->hw_domain);
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iounmap(irqc->base);
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kfree(irqc);
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return -ENODEV;
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}
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if (aic_init_smp(irqc, node))
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goto err_remove_domain;
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set_handle_irq(aic_handle_irq);
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set_handle_fiq(aic_handle_fiq);
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@ -1011,6 +1109,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
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off += irqc->info.die_stride;
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}
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if (irqc->info.version == 2) {
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u32 config = aic_ic_read(irqc, AIC2_CONFIG);
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config |= AIC2_CONFIG_ENABLE;
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aic_ic_write(irqc, AIC2_CONFIG, config);
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}
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if (!is_kernel_in_hyp_mode())
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pr_info("Kernel running in EL1, mapping interrupts");
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@ -1027,6 +1132,16 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
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irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI);
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return 0;
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err_remove_domain:
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irq_domain_remove(irqc->hw_domain);
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err_unmap:
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if (irqc->event && irqc->event != irqc->base)
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iounmap(irqc->event);
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iounmap(irqc->base);
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kfree(irqc);
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return -ENODEV;
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}
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IRQCHIP_DECLARE(apple_m1_aic, "apple,aic", aic_of_ic_init);
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IRQCHIP_DECLARE(apple_aic, "apple,aic", aic_of_ic_init);
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IRQCHIP_DECLARE(apple_aic2, "apple,aic2", aic_of_ic_init);
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