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pinctrl: rockchip: Add pinctrl support for PX30
There are 4 banks (GPIO0 ~ GPIO3), bank0 is in PD_PMU subsystem, bank1/bank2/bank3 are in PD_BUS subsystem. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
David Wu
Linus Walleij
parent
f61f5a2174
commit
87065ca9b8
@ -20,6 +20,7 @@ defined as gpio sub-nodes of the pinmux controller.
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Required properties for iomux controller:
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- compatible: should be
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"rockchip,px30-pinctrl": for Rockchip PX30
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"rockchip,rv1108-pinctrl": for Rockchip RV1108
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"rockchip,rk2928-pinctrl": for Rockchip RK2928
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"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
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@ -59,6 +59,7 @@
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#define GPIO_LS_SYNC 0x60
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enum rockchip_pinctrl_type {
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PX30,
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RV1108,
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RK2928,
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RK3066B,
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@ -701,6 +702,66 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
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*bit = data->bit;
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}
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static struct rockchip_mux_route_data px30_mux_route_data[] = {
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{
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/* cif-d2m0 */
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.bank_num = 2,
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.pin = 0,
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.func = 1,
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.route_offset = 0x184,
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.route_val = BIT(16 + 7),
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}, {
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/* cif-d2m1 */
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.bank_num = 3,
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.pin = 3,
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.func = 3,
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.route_offset = 0x184,
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.route_val = BIT(16 + 7) | BIT(7),
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}, {
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/* pdm-m0 */
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.bank_num = 3,
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.pin = 22,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 8),
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}, {
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/* pdm-m1 */
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.bank_num = 2,
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.pin = 22,
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.func = 1,
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.route_offset = 0x184,
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.route_val = BIT(16 + 8) | BIT(8),
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}, {
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/* uart2-rxm0 */
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.bank_num = 1,
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.pin = 27,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 10),
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}, {
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/* uart2-rxm1 */
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.bank_num = 2,
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.pin = 14,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 10) | BIT(10),
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}, {
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/* uart3-rxm0 */
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.bank_num = 0,
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.pin = 17,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 9),
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}, {
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/* uart3-rxm1 */
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.bank_num = 1,
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.pin = 15,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 9) | BIT(9),
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},
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};
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static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
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{
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/* spi-0 */
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@ -1202,6 +1263,97 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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return ret;
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}
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#define PX30_PULL_PMU_OFFSET 0x10
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#define PX30_PULL_GRF_OFFSET 0x60
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#define PX30_PULL_BITS_PER_PIN 2
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#define PX30_PULL_PINS_PER_REG 8
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#define PX30_PULL_BANK_STRIDE 16
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static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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/* The first 32 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = PX30_PULL_PMU_OFFSET;
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} else {
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*regmap = info->regmap_base;
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*reg = PX30_PULL_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
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}
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*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % PX30_PULL_PINS_PER_REG);
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*bit *= PX30_PULL_BITS_PER_PIN;
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}
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#define PX30_DRV_PMU_OFFSET 0x20
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#define PX30_DRV_GRF_OFFSET 0xf0
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#define PX30_DRV_BITS_PER_PIN 2
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#define PX30_DRV_PINS_PER_REG 8
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#define PX30_DRV_BANK_STRIDE 16
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static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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/* The first 32 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = PX30_DRV_PMU_OFFSET;
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} else {
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*regmap = info->regmap_base;
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*reg = PX30_DRV_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
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}
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*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % PX30_DRV_PINS_PER_REG);
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*bit *= PX30_DRV_BITS_PER_PIN;
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}
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#define PX30_SCHMITT_PMU_OFFSET 0x38
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#define PX30_SCHMITT_GRF_OFFSET 0xc0
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#define PX30_SCHMITT_PINS_PER_PMU_REG 16
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#define PX30_SCHMITT_BANK_STRIDE 16
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#define PX30_SCHMITT_PINS_PER_GRF_REG 8
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static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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int pins_per_reg;
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = PX30_SCHMITT_PMU_OFFSET;
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pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
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} else {
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*regmap = info->regmap_base;
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*reg = PX30_SCHMITT_GRF_OFFSET;
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pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
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*reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
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}
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*reg += ((pin_num / pins_per_reg) * 4);
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*bit = pin_num % pins_per_reg;
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return 0;
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}
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#define RV1108_PULL_PMU_OFFSET 0x10
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#define RV1108_PULL_OFFSET 0x110
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#define RV1108_PULL_PINS_PER_REG 8
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@ -1798,6 +1950,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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return !(data & BIT(bit))
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? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
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: PIN_CONFIG_BIAS_DISABLE;
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case PX30:
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case RV1108:
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case RK3188:
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case RK3288:
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@ -1841,6 +1994,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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data |= BIT(bit);
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ret = regmap_write(regmap, reg, data);
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break;
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case PX30:
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case RV1108:
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case RK3188:
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case RK3288:
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@ -2103,6 +2257,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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pull == PIN_CONFIG_BIAS_DISABLE);
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case RK3066B:
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return pull ? false : true;
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case PX30:
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case RV1108:
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case RK3188:
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case RK3288:
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@ -3237,6 +3392,43 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
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return 0;
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}
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static struct rockchip_pin_bank px30_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU
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),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT
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),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT
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),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT
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),
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};
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static struct rockchip_pin_ctrl px30_pin_ctrl = {
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.pin_banks = px30_pin_banks,
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.nr_banks = ARRAY_SIZE(px30_pin_banks),
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.label = "PX30-GPIO",
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.type = PX30,
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.grf_mux_offset = 0x0,
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.pmu_mux_offset = 0x0,
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.iomux_routes = px30_mux_route_data,
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.niomux_routes = ARRAY_SIZE(px30_mux_route_data),
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.pull_calc_reg = px30_calc_pull_reg_and_bit,
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.drv_calc_reg = px30_calc_drv_reg_and_bit,
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.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
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};
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static struct rockchip_pin_bank rv1108_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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@ -3545,6 +3737,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
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};
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static const struct of_device_id rockchip_pinctrl_dt_match[] = {
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{ .compatible = "rockchip,px30-pinctrl",
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.data = &px30_pin_ctrl },
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{ .compatible = "rockchip,rv1108-pinctrl",
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.data = &rv1108_pin_ctrl },
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{ .compatible = "rockchip,rk2928-pinctrl",
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