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drm fixes for 6.8-rc1

Browse Source 
i915:
 - Fixes for kernel-doc warnings enforced in linux-next
 - Another build warning fix for string formatting of intel_wakeref_t
 - Display fixes for DP DSC BPC and C20 PLL state verification
 
 v3d:
 - register readout fix
 
 rockchip:
 - two build warning fixes
 
 nouveau:
 - fix GSP loading on Turing with different nvdec configuration
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Merge tag 'drm-next-2024-01-15-1' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "This is just a wrap up of fixes from the last few days. It has the
  proper fix to the i915/xe collision, we can clean up what you did
  later once rc1 lands.

  Otherwise it's a few other i915, a v3d, rockchip and a nouveau fix to
  make GSP load on some original Turing GPUs.

  i915:
   - Fixes for kernel-doc warnings enforced in linux-next
   - Another build warning fix for string formatting of intel_wakeref_t
   - Display fixes for DP DSC BPC and C20 PLL state verification

  v3d:
   - register readout fix

  rockchip:
   - two build warning fixes

  nouveau:
   - fix GSP loading on Turing with different nvdec configuration"

* tag 'drm-next-2024-01-15-1' of git://anongit.freedesktop.org/drm/drm:
  nouveau/gsp: handle engines in runl without nonstall interrupts.
  drm/i915/perf: reconcile Excess struct member kernel-doc warnings
  drm/i915/guc: reconcile Excess struct member kernel-doc warnings
  drm/i915/gt: reconcile Excess struct member kernel-doc warnings
  drm/i915/gem: reconcile Excess struct member kernel-doc warnings
  drm/i915/dp: Fix the max DSC bpc supported by source
  drm/i915: don't make assumptions about intel_wakeref_t type
  drm/i915/dp: Fix the PSR debugfs entries wrt. MST connectors
  drm/i915/display: Fix C20 pll selection for state verification
  drm/v3d: Fix support for register debugging on the RPi 4
  drm/rockchip: vop2: Drop unused if_dclk_rate variable
  drm/rockchip: vop2: Drop superfluous include
This commit is contained in:
Linus Torvalds 2024-01-17 14:59:05 -08:00
commit 8893a6bfff
13 changed files with 96 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/drm/i915/display/intel_cx0_phy.c
View File

@ -3067,24 +3067,29 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20;
bool use_mplla;
bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB;
bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB;
int i;
use_mplla = intel_c20_use_mplla(mpll_hw_state->clock);
if (use_mplla) {
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
crtc->base.base.id, crtc->base.name, i,
mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
}
} else {
I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
"[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
crtc->base.base.id, crtc->base.name,
sw_use_mpllb, hw_use_mpllb);
if (hw_use_mpllb) {
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],
"[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
crtc->base.base.id, crtc->base.name, i,
mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
crtc->base.base.id, crtc->base.name, i,
mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
}
}
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {

4
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -405,8 +405,8 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
struct drm_i915_private,
display.power.domains);
drm_dbg(&i915->drm, "async_put_wakeref %lu\n",
power_domains->async_put_wakeref);
drm_dbg(&i915->drm, "async_put_wakeref: %s\n",
str_yes_no(power_domains->async_put_wakeref));
print_power_domains(power_domains, "async_put_domains[0]",
&power_domains->async_put_domains[0]);

2
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -2101,7 +2101,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
}
}
dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
if (!dsc_max_bpc)
return -EINVAL;

10
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -3319,11 +3319,11 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct dentry *root = connector->base.debugfs_entry;
if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) {
if (!(HAS_DP20(i915) &&
connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort))
return;
}
/* TODO: Add support for MST connectors as well. */
if ((connector->base.connector_type != DRM_MODE_CONNECTOR_eDP &&
connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||
connector->mst_port)
return;
debugfs_create_file("i915_psr_sink_status", 0444, root,
connector, &i915_psr_sink_status_fops);

4
drivers/gpu/drm/i915/gem/i915_gem_context_types.h
View File

@ -412,9 +412,9 @@ struct i915_gem_context {
/** @stale: tracks stale engines to be destroyed */
struct {
/** @lock: guards engines */
/** @stale.lock: guards engines */
spinlock_t lock;
/** @engines: list of stale engines */
/** @stale.engines: list of stale engines */
struct list_head engines;
} stale;
};

7
drivers/gpu/drm/i915/gt/intel_gsc.h
View File

@ -21,8 +21,11 @@ struct mei_aux_device;
/**
* struct intel_gsc - graphics security controller
*
* @gem_obj: scratch memory GSC operations
* @intf : gsc interface
* @intf: gsc interface
* @intf.adev: MEI aux. device for this @intf
* @intf.gem_obj: scratch memory GSC operations
* @intf.irq: IRQ for this device (%-1 for no IRQ)
* @intf.id: this interface's id number/index
*/
struct intel_gsc {
struct intel_gsc_intf {

75
drivers/gpu/drm/i915/gt/uc/intel_guc.h
View File

@ -105,61 +105,67 @@ struct intel_guc {
*/
struct {
/**
* @lock: protects everything in submission_state,
* ce->guc_id.id, and ce->guc_id.ref when transitioning in and
* out of zero
* @submission_state.lock: protects everything in
* submission_state, ce->guc_id.id, and ce->guc_id.ref
* when transitioning in and out of zero
*/
spinlock_t lock;
/**
* @guc_ids: used to allocate new guc_ids, single-lrc
* @submission_state.guc_ids: used to allocate new
* guc_ids, single-lrc
*/
struct ida guc_ids;
/**
* @num_guc_ids: Number of guc_ids, selftest feature to be able
* to reduce this number while testing.
* @submission_state.num_guc_ids: Number of guc_ids, selftest
* feature to be able to reduce this number while testing.
*/
int num_guc_ids;
/**
* @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
* @submission_state.guc_ids_bitmap: used to allocate
* new guc_ids, multi-lrc
*/
unsigned long *guc_ids_bitmap;
/**
* @guc_id_list: list of intel_context with valid guc_ids but no
* refs
* @submission_state.guc_id_list: list of intel_context
* with valid guc_ids but no refs
*/
struct list_head guc_id_list;
/**
* @guc_ids_in_use: Number single-lrc guc_ids in use
* @submission_state.guc_ids_in_use: Number single-lrc
* guc_ids in use
*/
unsigned int guc_ids_in_use;
/**
* @destroyed_contexts: list of contexts waiting to be destroyed
* (deregistered with the GuC)
* @submission_state.destroyed_contexts: list of contexts
* waiting to be destroyed (deregistered with the GuC)
*/
struct list_head destroyed_contexts;
/**
* @destroyed_worker: worker to deregister contexts, need as we
* need to take a GT PM reference and can't from destroy
* function as it might be in an atomic context (no sleeping)
* @submission_state.destroyed_worker: worker to deregister
* contexts, need as we need to take a GT PM reference and
* can't from destroy function as it might be in an atomic
* context (no sleeping)
*/
struct work_struct destroyed_worker;
/**
* @reset_fail_worker: worker to trigger a GT reset after an
* engine reset fails
* @submission_state.reset_fail_worker: worker to trigger
* a GT reset after an engine reset fails
*/
struct work_struct reset_fail_worker;
/**
* @reset_fail_mask: mask of engines that failed to reset
* @submission_state.reset_fail_mask: mask of engines that
* failed to reset
*/
intel_engine_mask_t reset_fail_mask;
/**
* @sched_disable_delay_ms: schedule disable delay, in ms, for
* contexts
* @submission_state.sched_disable_delay_ms: schedule
* disable delay, in ms, for contexts
*/
unsigned int sched_disable_delay_ms;
/**
* @sched_disable_gucid_threshold: threshold of min remaining available
* guc_ids before we start bypassing the schedule disable delay
* @submission_state.sched_disable_gucid_threshold:
* threshold of min remaining available guc_ids before
* we start bypassing the schedule disable delay
*/
unsigned int sched_disable_gucid_threshold;
} submission_state;
@ -243,37 +249,40 @@ struct intel_guc {
*/
struct {
/**
* @lock: Lock protecting the below fields and the engine stats.
* @timestamp.lock: Lock protecting the below fields and
* the engine stats.
*/
spinlock_t lock;
/**
* @gt_stamp: 64 bit extended value of the GT timestamp.
* @timestamp.gt_stamp: 64-bit extended value of the GT
* timestamp.
*/
u64 gt_stamp;
/**
* @ping_delay: Period for polling the GT timestamp for
* overflow.
* @timestamp.ping_delay: Period for polling the GT
* timestamp for overflow.
*/
unsigned long ping_delay;
/**
* @work: Periodic work to adjust GT timestamp, engine and
* context usage for overflows.
* @timestamp.work: Periodic work to adjust GT timestamp,
* engine and context usage for overflows.
*/
struct delayed_work work;
/**
* @shift: Right shift value for the gpm timestamp
* @timestamp.shift: Right shift value for the gpm timestamp
*/
u32 shift;
/**
* @last_stat_jiffies: jiffies at last actual stats collection time
* We use this timestamp to ensure we don't oversample the
* stats because runtime power management events can trigger
* stats collection at much higher rates than required.
* @timestamp.last_stat_jiffies: jiffies at last actual
* stats collection time. We use this timestamp to ensure
* we don't oversample the stats because runtime power
* management events can trigger stats collection at much
* higher rates than required.
*/
unsigned long last_stat_jiffies;
} timestamp;

9
drivers/gpu/drm/i915/i915_perf_types.h
View File

@ -291,7 +291,8 @@ struct i915_perf_stream {
int size_exponent;
/**
* @ptr_lock: Locks reads and writes to all head/tail state
* @oa_buffer.ptr_lock: Locks reads and writes to all
* head/tail state
*
* Consider: the head and tail pointer state needs to be read
* consistently from a hrtimer callback (atomic context) and
@ -313,7 +314,8 @@ struct i915_perf_stream {
spinlock_t ptr_lock;
/**
* @head: Although we can always read back the head pointer register,
* @oa_buffer.head: Although we can always read back
* the head pointer register,
* we prefer to avoid trusting the HW state, just to avoid any
* risk that some hardware condition could * somehow bump the
* head pointer unpredictably and cause us to forward the wrong
@ -322,7 +324,8 @@ struct i915_perf_stream {
u32 head;
/**
* @tail: The last verified tail that can be read by userspace.
* @oa_buffer.tail: The last verified tail that can be
* read by userspace.
*/
u32 tail;
} oa_buffer;

4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
View File

@ -550,6 +550,10 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)
struct nvkm_engn *engn = list_first_entry(&runl->engns, typeof(*engn), head);
runl->nonstall.vector = engn->func->nonstall(engn);
/* if no nonstall vector just keep going */
if (runl->nonstall.vector == -1)
continue;
if (runl->nonstall.vector < 0) {
RUNL_ERROR(runl, "nonstall %d", runl->nonstall.vector);
return runl->nonstall.vector;

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
View File

@ -351,7 +351,7 @@ r535_engn_nonstall(struct nvkm_engn *engn)
int ret;
ret = nvkm_gsp_intr_nonstall(subdev->device->gsp, subdev->type, subdev->inst);
WARN_ON(ret < 0);
WARN_ON(ret == -ENOENT);
return ret;
}

8
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
View File

@ -25,12 +25,8 @@ int
nvkm_gsp_intr_nonstall(struct nvkm_gsp *gsp, enum nvkm_subdev_type type, int inst)
{
for (int i = 0; i < gsp->intr_nr; i++) {
if (gsp->intr[i].type == type && gsp->intr[i].inst == inst) {
if (gsp->intr[i].nonstall != ~0)
return gsp->intr[i].nonstall;
return -EINVAL;
}
if (gsp->intr[i].type == type && gsp->intr[i].inst == inst)
return gsp->intr[i].nonstall;
}
return -ENOENT;

4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@ -35,7 +35,6 @@
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop2.h"
#include "rockchip_rgb.h"
@ -1681,7 +1680,6 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
unsigned long dclk_core_rate = v_pixclk >> 2;
unsigned long dclk_rate = v_pixclk;
unsigned long dclk_out_rate;
unsigned long if_dclk_rate;
unsigned long if_pixclk_rate;
int K = 1;
@ -1696,8 +1694,8 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
}
if_pixclk_rate = (dclk_core_rate << 1) / K;
if_dclk_rate = dclk_core_rate / K;
/*
* if_dclk_rate = dclk_core_rate / K;
* *if_pixclk_div = dclk_rate / if_pixclk_rate;
* *if_dclk_div = dclk_rate / if_dclk_rate;
*/

20
drivers/gpu/drm/v3d/v3d_debugfs.c
View File

@ -62,9 +62,9 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = {
REGDEF(33, 71, V3D_PTB_BPCA),
REGDEF(33, 71, V3D_PTB_BPCS),
REGDEF(33, 41, V3D_GMP_STATUS(33)),
REGDEF(33, 41, V3D_GMP_CFG(33)),
REGDEF(33, 41, V3D_GMP_VIO_ADDR(33)),
REGDEF(33, 42, V3D_GMP_STATUS(33)),
REGDEF(33, 42, V3D_GMP_CFG(33)),
REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
REGDEF(33, 71, V3D_ERR_FDBGO),
REGDEF(33, 71, V3D_ERR_FDBGB),
@ -74,13 +74,13 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = {
static const struct v3d_reg_def v3d_csd_reg_defs[] = {
REGDEF(41, 71, V3D_CSD_STATUS),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),