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drm/amd/display: Lock all enabled otg pipes even with no planes

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[WHY]
On DCN32 we support dynamic ODM even when OTG is blanked. When ODM
configuration is dynamically changed and the OTG is on blank pattern,
we will need to reprogram OPP's test pattern based on new ODM
configuration. Therefore we need to lock the OTG pipe to avoid temporary
corruption when we are reprogramming OPP blank patterns.

[HOW]
Add a new interdependent update lock implementation to lock all enabled
OTG pipes even when there is no plane on the OTG for DCN32.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu 2024-02-23 15:17:39 -05:00 committed by Alex Deucher
parent 8e054b0f1e
commit 94040c2cbb
3 changed files with 26 additions and 1 deletions
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23
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@ -1785,3 +1785,26 @@ void dcn32_prepare_bandwidth(struct dc *dc,
context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
}
}
void dcn32_interdependent_update_lock(struct dc *dc,
struct dc_state *context, bool lock)
{
unsigned int i;
struct pipe_ctx *pipe;
struct timing_generator *tg;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
tg = pipe->stream_res.tg;
if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
!tg->funcs->is_tg_enabled(tg) ||
dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
continue;
if (lock)
dc->hwss.pipe_control_lock(dc, pipe, true);
else
dc->hwss.pipe_control_lock(dc, pipe, false);
}
}

2
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
View File

@ -129,4 +129,6 @@ bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
void dcn32_prepare_bandwidth(struct dc *dc,
struct dc_state *context);
void dcn32_interdependent_update_lock(struct dc *dc,
struct dc_state *context, bool lock);
#endif /* __DC_HWSS_DCN32_H__ */

2
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
View File

@ -58,7 +58,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.disable_plane = dcn20_disable_plane,
.disable_pixel_data = dcn20_disable_pixel_data,
.pipe_control_lock = dcn20_pipe_control_lock,
.interdependent_update_lock = dcn10_lock_all_pipes,
.interdependent_update_lock = dcn32_interdependent_update_lock,
.cursor_lock = dcn10_cursor_lock,
.prepare_bandwidth = dcn32_prepare_bandwidth,
.optimize_bandwidth = dcn20_optimize_bandwidth,