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iio: dac: ad5360: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: a3e2940c24 ("staging:iio:dac: Add AD5360 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-45-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:24 +01:00
parent 8779b88c21
commit 94ec314e1b
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/dac/ad5360.c
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@ -79,13 +79,13 @@ struct ad5360_state {
struct mutex lock; struct mutex lock;
/* /*
* DMA (thus cache coherency maintenance) requires the * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines. * transfer buffers to live in their own cache lines.
*/ */
union { union {
__be32 d32; __be32 d32;
u8 d8[4]; u8 d8[4];
} data[2] ____cacheline_aligned; } data[2] __aligned(IIO_DMA_MINALIGN);
}; };
enum ad5360_type { enum ad5360_type {