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iio: gyro: adxrs450: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes tag is inaccurate but unlikely anyone will be interested in
backporting beyond that point.

Fixes: 53ac8500ba ("staging:iio:adxrs450: Move header file contents to main file")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-75-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:54 +01:00
parent ff3211b2ba
commit 966d2f4ee7
1 changed files with 1 additions and 1 deletions
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2
drivers/iio/gyro/adxrs450.c
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@ -73,7 +73,7 @@ enum {
struct adxrs450_state {
struct spi_device *us;
struct mutex buf_lock;
__be32 tx ____cacheline_aligned;
__be32 tx __aligned(IIO_DMA_MINALIGN);
__be32 rx;
};