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media fixes for v6.5-rc4

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Merge tag 'media/v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Pull media fixes from Mauro Carvalho Chehab:

 - some warning fixes

 - verisilicon: an excessive usage of stack fix and changes at reg
   access

 - amphion: use dev_err_probe

 - pulse8-cec: handle possible ping error

 - imx-jpeg: Support to assign slot for encoder/decoder

 - amphion: Fix firmware path to match linux-firmware

 - pci: cx23885: fix error handling for cx23885 ATSC boards

 - staging: atomisp: select V4L2_FWNODE

 - mediatek: vcodec: fix cancel_work_sync fail with fluster test

* tag 'media/v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media:
  media: verisilicon: change confusingly named relaxed register access
  media: verisilicon: fix excessive stack usage
  media: mediatek: vcodec: fix cancel_work_sync fail with fluster test
  media: pci: cx23885: fix error handling for cx23885 ATSC boards
  media: pulse8-cec: handle possible ping error
  media: mtk_jpeg_core: avoid unused-variable warning
  media: imx-jpeg: Support to assign slot for encoder/decoder
  media: amphion: Fix firmware path to match linux-firmware
  media: amphion: use dev_err_probe
  media: staging: atomisp: select V4L2_FWNODE
  media: tc358746: Address compiler warnings
This commit is contained in:
Linus Torvalds 2023-07-24 09:25:18 -07:00
commit 9e0ee0c754
15 changed files with 118 additions and 139 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/media/cec/usb/pulse8/pulse8-cec.c
View File

@ -809,8 +809,11 @@ static void pulse8_ping_eeprom_work_handler(struct work_struct *work)
mutex_lock(&pulse8->lock);
cmd = MSGCODE_PING;
pulse8_send_and_wait(pulse8, &cmd, 1,
MSGCODE_COMMAND_ACCEPTED, 0);
if (pulse8_send_and_wait(pulse8, &cmd, 1,
MSGCODE_COMMAND_ACCEPTED, 0)) {
dev_warn(pulse8->dev, "failed to ping EEPROM\n");
goto unlock;
}
if (pulse8->vers < 2)
goto unlock;

4
drivers/media/i2c/tc358746.c
View File

@ -813,8 +813,8 @@ static unsigned long tc358746_find_pll_settings(struct tc358746 *tc358746,
u32 min_delta = 0xffffffff;
u16 prediv_max = 17;
u16 prediv_min = 1;
u16 m_best, mul;
u16 p_best, p;
u16 m_best = 0, mul;
u16 p_best = 1, p;
u8 postdiv;
if (fout > 1000 * HZ_PER_MHZ) {

12
drivers/media/pci/cx23885/cx23885-dvb.c
View File

@ -2459,16 +2459,10 @@ static int dvb_register(struct cx23885_tsport *port)
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
@ -2505,16 +2499,10 @@ static int dvb_register(struct cx23885_tsport *port)
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;

4
drivers/media/platform/amphion/vpu_core.c
View File

@ -826,7 +826,7 @@ static const struct dev_pm_ops vpu_core_pm_ops = {
static struct vpu_core_resources imx8q_enc = {
.type = VPU_CORE_TYPE_ENC,
.fwname = "vpu/vpu_fw_imx8_enc.bin",
.fwname = "amphion/vpu/vpu_fw_imx8_enc.bin",
.stride = 16,
.max_width = 1920,
.max_height = 1920,
@ -841,7 +841,7 @@ static struct vpu_core_resources imx8q_enc = {
static struct vpu_core_resources imx8q_dec = {
.type = VPU_CORE_TYPE_DEC,
.fwname = "vpu/vpu_fw_imx8_dec.bin",
.fwname = "amphion/vpu/vpu_fw_imx8_dec.bin",
.stride = 256,
.max_width = 8188,
.max_height = 8188,

9
drivers/media/platform/amphion/vpu_mbox.c
View File

@ -46,11 +46,10 @@ static int vpu_mbox_request_channel(struct device *dev, struct vpu_mbox *mbox)
cl->rx_callback = vpu_mbox_rx_callback;
ch = mbox_request_channel_byname(cl, mbox->name);
if (IS_ERR(ch)) {
dev_err(dev, "Failed to request mbox chan %s, ret : %ld\n",
mbox->name, PTR_ERR(ch));
return PTR_ERR(ch);
}
if (IS_ERR(ch))
return dev_err_probe(dev, PTR_ERR(ch),
"Failed to request mbox chan %s\n",
mbox->name);
mbox->ch = ch;
return 0;

6
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
View File

@ -28,7 +28,6 @@
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_parse.h"
#if defined(CONFIG_OF)
static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
{
.fourcc = V4L2_PIX_FMT_JPEG,
@ -102,7 +101,6 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
.flags = MTK_JPEG_FMT_FLAG_CAPTURE,
},
};
#endif
#define MTK_JPEG_ENC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_enc_formats)
#define MTK_JPEG_DEC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_dec_formats)
@ -1455,7 +1453,6 @@ static const struct dev_pm_ops mtk_jpeg_pm_ops = {
SET_RUNTIME_PM_OPS(mtk_jpeg_pm_suspend, mtk_jpeg_pm_resume, NULL)
};
#if defined(CONFIG_OF)
static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx)
{
struct mtk_jpegenc_comp_dev *comp_jpeg;
@ -1951,14 +1948,13 @@ static const struct of_device_id mtk_jpeg_match[] = {
};
MODULE_DEVICE_TABLE(of, mtk_jpeg_match);
#endif
static struct platform_driver mtk_jpeg_driver = {
.probe = mtk_jpeg_probe,
.remove_new = mtk_jpeg_remove,
.driver = {
.name = MTK_JPEG_NAME,
.of_match_table = of_match_ptr(mtk_jpeg_match),
.of_match_table = mtk_jpeg_match,
.pm = &mtk_jpeg_pm_ops,
},
};

4
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
View File

@ -39,7 +39,6 @@ enum mtk_jpeg_color {
MTK_JPEG_COLOR_400 = 0x00110000
};
#if defined(CONFIG_OF)
static const struct of_device_id mtk_jpegdec_hw_ids[] = {
{
.compatible = "mediatek,mt8195-jpgdec-hw",
@ -47,7 +46,6 @@ static const struct of_device_id mtk_jpegdec_hw_ids[] = {
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
#endif
static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
{
@ -653,7 +651,7 @@ static struct platform_driver mtk_jpegdec_hw_driver = {
.probe = mtk_jpegdec_hw_probe,
.driver = {
.name = "mtk-jpegdec-hw",
.of_match_table = of_match_ptr(mtk_jpegdec_hw_ids),
.of_match_table = mtk_jpegdec_hw_ids,
},
};

4
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
View File

@ -46,7 +46,6 @@ static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] = {
{.quality_param = 97, .hardware_value = JPEG_ENC_QUALITY_Q97},
};
#if defined(CONFIG_OF)
static const struct of_device_id mtk_jpegenc_drv_ids[] = {
{
.compatible = "mediatek,mt8195-jpgenc-hw",
@ -54,7 +53,6 @@ static const struct of_device_id mtk_jpegenc_drv_ids[] = {
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
#endif
void mtk_jpeg_enc_reset(void __iomem *base)
{
@ -377,7 +375,7 @@ static struct platform_driver mtk_jpegenc_hw_driver = {
.probe = mtk_jpegenc_hw_probe,
.driver = {
.name = "mtk-jpegenc-hw",
.of_match_table = of_match_ptr(mtk_jpegenc_drv_ids),
.of_match_table = mtk_jpegenc_drv_ids,
},
};

3
drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c
View File

@ -233,7 +233,8 @@ void vdec_msg_queue_deinit(struct vdec_msg_queue *msg_queue,
kfree(lat_buf->private_data);
}
cancel_work_sync(&msg_queue->core_work);
if (msg_queue->wdma_addr.size)
cancel_work_sync(&msg_queue->core_work);
}
static void vdec_msg_queue_core_work(struct work_struct *work)

1
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.h
View File

@ -58,7 +58,6 @@
#define CAST_OFBSIZE_LO CAST_STATUS18
#define CAST_OFBSIZE_HI CAST_STATUS19
#define MXC_MAX_SLOTS 1 /* TODO use all 4 slots*/
/* JPEG-Decoder Wrapper Slot Registers 0..3 */
#define SLOT_BASE 0x10000
#define SLOT_STATUS 0x0

135
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
View File

@ -745,87 +745,77 @@ static void notify_src_chg(struct mxc_jpeg_ctx *ctx)
v4l2_event_queue_fh(&ctx->fh, &ev);
}
static int mxc_get_free_slot(struct mxc_jpeg_slot_data slot_data[], int n)
static int mxc_get_free_slot(struct mxc_jpeg_slot_data *slot_data)
{
int free_slot = 0;
while (slot_data[free_slot].used && free_slot < n)
free_slot++;
return free_slot; /* >=n when there are no more free slots */
if (!slot_data->used)
return slot_data->slot;
return -1;
}
static bool mxc_jpeg_alloc_slot_data(struct mxc_jpeg_dev *jpeg,
unsigned int slot)
static bool mxc_jpeg_alloc_slot_data(struct mxc_jpeg_dev *jpeg)
{
struct mxc_jpeg_desc *desc;
struct mxc_jpeg_desc *cfg_desc;
void *cfg_stm;
if (jpeg->slot_data[slot].desc)
if (jpeg->slot_data.desc)
goto skip_alloc; /* already allocated, reuse it */
/* allocate descriptor for decoding/encoding phase */
desc = dma_alloc_coherent(jpeg->dev,
sizeof(struct mxc_jpeg_desc),
&jpeg->slot_data[slot].desc_handle,
&jpeg->slot_data.desc_handle,
GFP_ATOMIC);
if (!desc)
goto err;
jpeg->slot_data[slot].desc = desc;
jpeg->slot_data.desc = desc;
/* allocate descriptor for configuration phase (encoder only) */
cfg_desc = dma_alloc_coherent(jpeg->dev,
sizeof(struct mxc_jpeg_desc),
&jpeg->slot_data[slot].cfg_desc_handle,
&jpeg->slot_data.cfg_desc_handle,
GFP_ATOMIC);
if (!cfg_desc)
goto err;
jpeg->slot_data[slot].cfg_desc = cfg_desc;
jpeg->slot_data.cfg_desc = cfg_desc;
/* allocate configuration stream */
cfg_stm = dma_alloc_coherent(jpeg->dev,
MXC_JPEG_MAX_CFG_STREAM,
&jpeg->slot_data[slot].cfg_stream_handle,
&jpeg->slot_data.cfg_stream_handle,
GFP_ATOMIC);
if (!cfg_stm)
goto err;
jpeg->slot_data[slot].cfg_stream_vaddr = cfg_stm;
jpeg->slot_data.cfg_stream_vaddr = cfg_stm;
skip_alloc:
jpeg->slot_data[slot].used = true;
jpeg->slot_data.used = true;
return true;
err:
dev_err(jpeg->dev, "Could not allocate descriptors for slot %d", slot);
dev_err(jpeg->dev, "Could not allocate descriptors for slot %d", jpeg->slot_data.slot);
return false;
}
static void mxc_jpeg_free_slot_data(struct mxc_jpeg_dev *jpeg,
unsigned int slot)
static void mxc_jpeg_free_slot_data(struct mxc_jpeg_dev *jpeg)
{
if (slot >= MXC_MAX_SLOTS) {
dev_err(jpeg->dev, "Invalid slot %d, nothing to free.", slot);
return;
}
/* free descriptor for decoding/encoding phase */
dma_free_coherent(jpeg->dev, sizeof(struct mxc_jpeg_desc),
jpeg->slot_data[slot].desc,
jpeg->slot_data[slot].desc_handle);
jpeg->slot_data.desc,
jpeg->slot_data.desc_handle);
/* free descriptor for encoder configuration phase / decoder DHT */
dma_free_coherent(jpeg->dev, sizeof(struct mxc_jpeg_desc),
jpeg->slot_data[slot].cfg_desc,
jpeg->slot_data[slot].cfg_desc_handle);
jpeg->slot_data.cfg_desc,
jpeg->slot_data.cfg_desc_handle);
/* free configuration stream */
dma_free_coherent(jpeg->dev, MXC_JPEG_MAX_CFG_STREAM,
jpeg->slot_data[slot].cfg_stream_vaddr,
jpeg->slot_data[slot].cfg_stream_handle);
jpeg->slot_data.cfg_stream_vaddr,
jpeg->slot_data.cfg_stream_handle);
jpeg->slot_data[slot].used = false;
jpeg->slot_data.used = false;
}
static void mxc_jpeg_check_and_set_last_buffer(struct mxc_jpeg_ctx *ctx,
@ -855,7 +845,7 @@ static void mxc_jpeg_job_finish(struct mxc_jpeg_ctx *ctx, enum vb2_buffer_state
v4l2_m2m_buf_done(dst_buf, state);
mxc_jpeg_disable_irq(reg, ctx->slot);
ctx->mxc_jpeg->slot_data[ctx->slot].used = false;
jpeg->slot_data.used = false;
if (reset)
mxc_jpeg_sw_reset(reg);
}
@ -919,7 +909,7 @@ static irqreturn_t mxc_jpeg_dec_irq(int irq, void *priv)
goto job_unlock;
}
if (!jpeg->slot_data[slot].used)
if (!jpeg->slot_data.used)
goto job_unlock;
dec_ret = readl(reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
@ -1179,13 +1169,13 @@ static void mxc_jpeg_config_dec_desc(struct vb2_buffer *out_buf,
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
void __iomem *reg = jpeg->base_reg;
unsigned int slot = ctx->slot;
struct mxc_jpeg_desc *desc = jpeg->slot_data[slot].desc;
struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data[slot].cfg_desc;
dma_addr_t desc_handle = jpeg->slot_data[slot].desc_handle;
dma_addr_t cfg_desc_handle = jpeg->slot_data[slot].cfg_desc_handle;
dma_addr_t cfg_stream_handle = jpeg->slot_data[slot].cfg_stream_handle;
unsigned int *cfg_size = &jpeg->slot_data[slot].cfg_stream_size;
void *cfg_stream_vaddr = jpeg->slot_data[slot].cfg_stream_vaddr;
struct mxc_jpeg_desc *desc = jpeg->slot_data.desc;
struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data.cfg_desc;
dma_addr_t desc_handle = jpeg->slot_data.desc_handle;
dma_addr_t cfg_desc_handle = jpeg->slot_data.cfg_desc_handle;
dma_addr_t cfg_stream_handle = jpeg->slot_data.cfg_stream_handle;
unsigned int *cfg_size = &jpeg->slot_data.cfg_stream_size;
void *cfg_stream_vaddr = jpeg->slot_data.cfg_stream_vaddr;
struct mxc_jpeg_src_buf *jpeg_src_buf;
jpeg_src_buf = vb2_to_mxc_buf(src_buf);
@ -1245,18 +1235,18 @@ static void mxc_jpeg_config_enc_desc(struct vb2_buffer *out_buf,
struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg;
void __iomem *reg = jpeg->base_reg;
unsigned int slot = ctx->slot;
struct mxc_jpeg_desc *desc = jpeg->slot_data[slot].desc;
struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data[slot].cfg_desc;
dma_addr_t desc_handle = jpeg->slot_data[slot].desc_handle;
dma_addr_t cfg_desc_handle = jpeg->slot_data[slot].cfg_desc_handle;
void *cfg_stream_vaddr = jpeg->slot_data[slot].cfg_stream_vaddr;
struct mxc_jpeg_desc *desc = jpeg->slot_data.desc;
struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data.cfg_desc;
dma_addr_t desc_handle = jpeg->slot_data.desc_handle;
dma_addr_t cfg_desc_handle = jpeg->slot_data.cfg_desc_handle;
void *cfg_stream_vaddr = jpeg->slot_data.cfg_stream_vaddr;
struct mxc_jpeg_q_data *q_data;
enum mxc_jpeg_image_format img_fmt;
int w, h;
q_data = mxc_jpeg_get_q_data(ctx, src_buf->vb2_queue->type);
jpeg->slot_data[slot].cfg_stream_size =
jpeg->slot_data.cfg_stream_size =
mxc_jpeg_setup_cfg_stream(cfg_stream_vaddr,
q_data->fmt->fourcc,
q_data->crop.width,
@ -1265,7 +1255,7 @@ static void mxc_jpeg_config_enc_desc(struct vb2_buffer *out_buf,
/* chain the config descriptor with the encoding descriptor */
cfg_desc->next_descpt_ptr = desc_handle | MXC_NXT_DESCPT_EN;
cfg_desc->buf_base0 = jpeg->slot_data[slot].cfg_stream_handle;
cfg_desc->buf_base0 = jpeg->slot_data.cfg_stream_handle;
cfg_desc->buf_base1 = 0;
cfg_desc->line_pitch = 0;
cfg_desc->stm_bufbase = 0; /* no output expected */
@ -1408,7 +1398,7 @@ static void mxc_jpeg_device_run_timeout(struct work_struct *work)
unsigned long flags;
spin_lock_irqsave(&ctx->mxc_jpeg->hw_lock, flags);
if (ctx->slot < MXC_MAX_SLOTS && ctx->mxc_jpeg->slot_data[ctx->slot].used) {
if (ctx->mxc_jpeg->slot_data.used) {
dev_warn(jpeg->dev, "%s timeout, cancel it\n",
ctx->mxc_jpeg->mode == MXC_JPEG_DECODE ? "decode" : "encode");
mxc_jpeg_job_finish(ctx, VB2_BUF_STATE_ERROR, true);
@ -1476,12 +1466,12 @@ static void mxc_jpeg_device_run(void *priv)
mxc_jpeg_enable(reg);
mxc_jpeg_set_l_endian(reg, 1);
ctx->slot = mxc_get_free_slot(jpeg->slot_data, MXC_MAX_SLOTS);
if (ctx->slot >= MXC_MAX_SLOTS) {
ctx->slot = mxc_get_free_slot(&jpeg->slot_data);
if (ctx->slot < 0) {
dev_err(dev, "No more free slots\n");
goto end;
}
if (!mxc_jpeg_alloc_slot_data(jpeg, ctx->slot)) {
if (!mxc_jpeg_alloc_slot_data(jpeg)) {
dev_err(dev, "Cannot allocate slot data\n");
goto end;
}
@ -2101,7 +2091,7 @@ static int mxc_jpeg_open(struct file *file)
}
ctx->fh.ctrl_handler = &ctx->ctrl_handler;
mxc_jpeg_set_default_params(ctx);
ctx->slot = MXC_MAX_SLOTS; /* slot not allocated yet */
ctx->slot = -1; /* slot not allocated yet */
INIT_DELAYED_WORK(&ctx->task_timer, mxc_jpeg_device_run_timeout);
if (mxc_jpeg->mode == MXC_JPEG_DECODE)
@ -2677,6 +2667,11 @@ static int mxc_jpeg_attach_pm_domains(struct mxc_jpeg_dev *jpeg)
dev_err(dev, "No power domains defined for jpeg node\n");
return jpeg->num_domains;
}
if (jpeg->num_domains == 1) {
/* genpd_dev_pm_attach() attach automatically if power domains count is 1 */
jpeg->num_domains = 0;
return 0;
}
jpeg->pd_dev = devm_kmalloc_array(dev, jpeg->num_domains,
sizeof(*jpeg->pd_dev), GFP_KERNEL);
@ -2718,7 +2713,6 @@ static int mxc_jpeg_probe(struct platform_device *pdev)
int ret;
int mode;
const struct of_device_id *of_id;
unsigned int slot;
of_id = of_match_node(mxc_jpeg_match, dev->of_node);
if (!of_id)
@ -2742,19 +2736,22 @@ static int mxc_jpeg_probe(struct platform_device *pdev)
if (IS_ERR(jpeg->base_reg))
return PTR_ERR(jpeg->base_reg);
for (slot = 0; slot < MXC_MAX_SLOTS; slot++) {
dec_irq = platform_get_irq(pdev, slot);
if (dec_irq < 0) {
ret = dec_irq;
goto err_irq;
}
ret = devm_request_irq(&pdev->dev, dec_irq, mxc_jpeg_dec_irq,
0, pdev->name, jpeg);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq %d (%d)\n",
dec_irq, ret);
goto err_irq;
}
ret = of_property_read_u32_index(pdev->dev.of_node, "slot", 0, &jpeg->slot_data.slot);
if (ret)
jpeg->slot_data.slot = 0;
dev_info(&pdev->dev, "choose slot %d\n", jpeg->slot_data.slot);
dec_irq = platform_get_irq(pdev, 0);
if (dec_irq < 0) {
dev_err(&pdev->dev, "Failed to get irq %d\n", dec_irq);
ret = dec_irq;
goto err_irq;
}
ret = devm_request_irq(&pdev->dev, dec_irq, mxc_jpeg_dec_irq,
0, pdev->name, jpeg);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq %d (%d)\n",
dec_irq, ret);
goto err_irq;
}
jpeg->pdev = pdev;
@ -2914,11 +2911,9 @@ static const struct dev_pm_ops mxc_jpeg_pm_ops = {
static void mxc_jpeg_remove(struct platform_device *pdev)
{
unsigned int slot;
struct mxc_jpeg_dev *jpeg = platform_get_drvdata(pdev);
for (slot = 0; slot < MXC_MAX_SLOTS; slot++)
mxc_jpeg_free_slot_data(jpeg, slot);
mxc_jpeg_free_slot_data(jpeg);
pm_runtime_disable(&pdev->dev);
video_unregister_device(jpeg->dec_vdev);

5
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h
View File

@ -97,7 +97,7 @@ struct mxc_jpeg_ctx {
struct mxc_jpeg_q_data cap_q;
struct v4l2_fh fh;
enum mxc_jpeg_enc_state enc_state;
unsigned int slot;
int slot;
unsigned int source_change;
bool header_parsed;
struct v4l2_ctrl_handler ctrl_handler;
@ -106,6 +106,7 @@ struct mxc_jpeg_ctx {
};
struct mxc_jpeg_slot_data {
int slot;
bool used;
struct mxc_jpeg_desc *desc; // enc/dec descriptor
struct mxc_jpeg_desc *cfg_desc; // configuration descriptor
@ -128,7 +129,7 @@ struct mxc_jpeg_dev {
struct v4l2_device v4l2_dev;
struct v4l2_m2m_dev *m2m_dev;
struct video_device *dec_vdev;
struct mxc_jpeg_slot_data slot_data[MXC_MAX_SLOTS];
struct mxc_jpeg_slot_data slot_data;
int num_domains;
struct device **pd_dev;
struct device_link **pd_link;

50
drivers/media/platform/verisilicon/hantro.h
View File

@ -370,26 +370,26 @@ extern int hantro_debug;
pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
/* Structure access helpers. */
static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
static __always_inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
{
return container_of(fh, struct hantro_ctx, fh);
}
/* Register accessors. */
static inline void vepu_write_relaxed(struct hantro_dev *vpu,
u32 val, u32 reg)
static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu,
u32 val, u32 reg)
{
vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
writel_relaxed(val, vpu->enc_base + reg);
}
static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
{
vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
writel(val, vpu->enc_base + reg);
}
static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
{
u32 val = readl(vpu->enc_base + reg);
@ -397,27 +397,27 @@ static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
return val;
}
static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
u32 val, u32 reg)
static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu,
u32 val, u32 reg)
{
vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
writel_relaxed(val, vpu->dec_base + reg);
}
static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
{
vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
writel(val, vpu->dec_base + reg);
}
static inline void hantro_write_addr(struct hantro_dev *vpu,
unsigned long offset,
dma_addr_t addr)
static __always_inline void hantro_write_addr(struct hantro_dev *vpu,
unsigned long offset,
dma_addr_t addr)
{
vdpu_write(vpu, addr & 0xffffffff, offset);
}
static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
{
u32 val = readl(vpu->dec_base + reg);
@ -425,9 +425,9 @@ static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
return val;
}
static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
const struct hantro_reg *reg,
u32 val)
static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu,
const struct hantro_reg *reg,
u32 val)
{
u32 v;
@ -437,20 +437,20 @@ static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
return v;
}
static inline void hantro_reg_write(struct hantro_dev *vpu,
const struct hantro_reg *reg,
u32 val)
{
vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
}
static inline void hantro_reg_write_s(struct hantro_dev *vpu,
const struct hantro_reg *reg,
u32 val)
static __always_inline void hantro_reg_write(struct hantro_dev *vpu,
const struct hantro_reg *reg,
u32 val)
{
vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
}
static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu,
const struct hantro_reg *reg,
u32 val)
{
vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
}
void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);

12
drivers/media/platform/verisilicon/hantro_postproc.c
View File

@ -21,11 +21,11 @@
val); \
}
#define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \
#define HANTRO_PP_REG_WRITE_RELAXED(vpu, reg_name, val) \
{ \
hantro_reg_write_s(vpu, \
&hantro_g1_postproc_regs.reg_name, \
val); \
hantro_reg_write_relaxed(vpu, \
&hantro_g1_postproc_regs.reg_name, \
val); \
}
#define VPU_PP_IN_YUYV 0x0
@ -72,7 +72,7 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
dma_addr_t dst_dma;
/* Turn on pipeline mode. Must be done first. */
HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x1);
src_pp_fmt = VPU_PP_IN_NV12;
@ -242,7 +242,7 @@ static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x0);
}
static void hantro_postproc_g2_disable(struct hantro_ctx *ctx)

1
drivers/staging/media/atomisp/Kconfig
View File

@ -13,6 +13,7 @@ config VIDEO_ATOMISP
tristate "Intel Atom Image Signal Processor Driver"
depends on VIDEO_DEV && INTEL_ATOMISP
depends on PMIC_OPREGION
select V4L2_FWNODE
select IOSF_MBI
select VIDEOBUF2_VMALLOC
select VIDEO_V4L2_SUBDEV_API