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iio: accel: sca3000: Fix alignment for DMA safety

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____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.

The second alignment marking is left in place to avoid doing more than
the simple fix in this patch.

Fixes: ced5c03d36 ("staging:iio:accel:sca3000 merge files into one.")
Fixes: 152a6a884a ("staging:iio:accel:sca3000 move to hybrid hard / soft buffer design.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-8-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:55:47 +01:00
parent a794b34083
commit a263456f0e
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/accel/sca3000.c
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@ -167,8 +167,8 @@ struct sca3000_state {
int mo_det_use_count;
struct mutex lock;
/* Can these share a cacheline ? */
u8 rx[384] ____cacheline_aligned;
u8 tx[6] ____cacheline_aligned;
u8 rx[384] __aligned(IIO_DMA_MINALIGN);
u8 tx[6] __aligned(IIO_DMA_MINALIGN);
};
/**