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[MTD] NAND: Add ST chip IDs.
From: Domenico DI TULLIO <domenico.di-tullio@st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -2,8 +2,8 @@
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* drivers/mtd/nandids.c
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*
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* Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
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*
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* $Id: nand_ids.c,v 1.12 2005/02/16 09:33:27 gleixner Exp $
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*
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* $Id: nand_ids.c,v 1.14 2005/06/23 09:38:50 gleixner Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -56,15 +56,24 @@ struct nand_flash_dev nand_flash_ids[] = {
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{"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
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{"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
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{"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
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{"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
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/* These are the new chips with large page size. The pagesize
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* and the erasesize is determined from the extended id bytes
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*/
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/*512 Megabit */
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{"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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{"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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/* 1 Gigabit */
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{"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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