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net: dsa: mt7530: Add the support of MT7531 switch
Add new support for MT7531:
MT7531 is the next generation of MT7530. It is also a 7-ports switch with
5 giga embedded phys, 2 cpu ports, and the same MAC logic of MT7530. Cpu
port 6 only supports SGMII interface. Cpu port 5 supports either RGMII
or SGMII in different HW sku, but cannot be muxed to PHY of port 0/4 like
mt7530. Due to SGMII interface support, pll, and pad setting are different
from MT7530. This patch adds different initial setting, and SGMII phylink
handlers of MT7531.
MT7531 SGMII interface can be configured in following mode:
- 'SGMII AN mode' with in-band negotiation capability
which is compatible with PHY_INTERFACE_MODE_SGMII.
- 'SGMII force mode' without in-band negotiation
which is compatible with 10B/8B encoding of
PHY_INTERFACE_MODE_1000BASEX with fixed full-duplex and fixed pause.
- 2.5 times faster clocked 'SGMII force mode' without in-band negotiation
which is compatible with 10B/8B encoding of
PHY_INTERFACE_MODE_2500BASEX with fixed full-duplex and fixed pause.
Signed-off-by: Landen Chao <landen.chao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Landen Chao
David S. Miller
parent
27834b0223
commit
c288575f78
@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
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the xrx200 / VR9 SoC.
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config NET_DSA_MT7530
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tristate "MediaTek MT7530 and MT7621 Ethernet switch support"
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tristate "MediaTek MT753x and MT7621 Ethernet switch support"
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depends on NET_DSA
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select NET_DSA_TAG_MTK
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help
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This enables support for the MediaTek MT7530 and MT7621 Ethernet
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switch chip.
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This enables support for the MediaTek MT7530, MT7531, and MT7621
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Ethernet switch chips.
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config NET_DSA_MV88E6060
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tristate "Marvell 88E6060 ethernet switch chip support"
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File diff suppressed because it is too large
Load Diff
@ -14,6 +14,7 @@
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enum mt753x_id {
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ID_MT7530 = 0,
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ID_MT7621 = 1,
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ID_MT7531 = 2,
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};
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#define NUM_TRGMII_CTRL 5
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@ -41,6 +42,33 @@ enum mt753x_id {
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#define MIRROR_PORT(x) ((x) & 0x7)
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#define MIRROR_MASK 0x7
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/* Registers for CPU forward control */
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#define MT7531_CFC 0x4
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#define MT7531_MIRROR_EN BIT(19)
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#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
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#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
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#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
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#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
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#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
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MT7531_CFC : MT7530_MFC)
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#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
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MT7531_MIRROR_EN : MIRROR_EN)
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#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
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MT7531_MIRROR_MASK : MIRROR_MASK)
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/* Registers for BPDU and PAE frame control*/
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#define MT753X_BPC 0x24
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#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
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enum mt753x_bpdu_port_fw {
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MT753X_BPDU_FOLLOW_MFC,
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MT753X_BPDU_CPU_EXCLUDE = 4,
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MT753X_BPDU_CPU_INCLUDE = 5,
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MT753X_BPDU_CPU_ONLY = 6,
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MT753X_BPDU_DROP = 7,
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};
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/* Registers for address table access */
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#define MT7530_ATA1 0x74
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#define STATIC_EMP 0
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@ -220,10 +248,30 @@ enum mt7530_vlan_port_attr {
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#define PMCR_FORCE_LNK BIT(0)
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#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
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PMCR_FORCE_SPEED_1000)
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#define MT7531_FORCE_LNK BIT(31)
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#define MT7531_FORCE_SPD BIT(30)
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#define MT7531_FORCE_DPX BIT(29)
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#define MT7531_FORCE_RX_FC BIT(28)
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#define MT7531_FORCE_TX_FC BIT(27)
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#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
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MT7531_FORCE_SPD | \
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MT7531_FORCE_DPX | \
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MT7531_FORCE_RX_FC | \
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MT7531_FORCE_TX_FC)
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#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
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MT7531_FORCE_MODE : \
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PMCR_FORCE_MODE)
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#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
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PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
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PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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PMCR_FORCE_FDX | PMCR_FORCE_LNK)
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#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
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PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
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PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
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PMCR_TX_EN | PMCR_RX_EN | \
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PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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PMCR_FORCE_SPEED_1000 | \
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PMCR_FORCE_FDX | PMCR_FORCE_LNK)
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#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
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#define PMSR_EEE1G BIT(7)
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@ -237,6 +285,10 @@ enum mt7530_vlan_port_attr {
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#define PMSR_DPX BIT(1)
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#define PMSR_LINK BIT(0)
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/* Register for port debug count */
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#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
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#define MT7531_DIS_CLR BIT(31)
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/* Register for MIB */
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#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
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#define MT7530_MIB_CCR 0x4fe0
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@ -254,12 +306,118 @@ enum mt7530_vlan_port_attr {
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CCR_RX_OCT_CNT_BAD | \
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CCR_TX_OCT_CNT_GOOD | \
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CCR_TX_OCT_CNT_BAD)
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/* MT7531 SGMII register group */
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#define MT7531_SGMII_REG_BASE 0x5000
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#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
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((p) - 5) * 0x1000 + (r))
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/* Register forSGMII PCS_CONTROL_1 */
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#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
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#define MT7531_SGMII_LINK_STATUS BIT(18)
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#define MT7531_SGMII_AN_ENABLE BIT(12)
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#define MT7531_SGMII_AN_RESTART BIT(9)
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/* Register for SGMII PCS_SPPED_ABILITY */
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#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
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#define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
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#define MT7531_SGMII_TX_CONFIG BIT(0)
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/* Register for SGMII_MODE */
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#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
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#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
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#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
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#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
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#define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
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#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
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#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
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#define MT7531_SGMII_FORCE_SPEED_10 0
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#define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
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enum mt7531_sgmii_force_duplex {
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MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
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MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
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};
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/* Fields of QPHY_PWR_STATE_CTRL */
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#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
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#define MT7531_SGMII_PHYA_PWD BIT(4)
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/* Values of SGMII SPEED */
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#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
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#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
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#define MT7531_RG_TPHY_SPEED_1_25G 0x0
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#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
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/* Register for system reset */
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#define MT7530_SYS_CTRL 0x7000
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#define SYS_CTRL_PHY_RST BIT(2)
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#define SYS_CTRL_SW_RST BIT(1)
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#define SYS_CTRL_REG_RST BIT(0)
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/* Register for PHY Indirect Access Control */
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#define MT7531_PHY_IAC 0x701C
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#define MT7531_PHY_ACS_ST BIT(31)
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#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
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#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
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#define MT7531_MDIO_CMD_MASK (0x3 << 18)
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#define MT7531_MDIO_ST_MASK (0x3 << 16)
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#define MT7531_MDIO_RW_DATA_MASK (0xffff)
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#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
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#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
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#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
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#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
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#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
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enum mt7531_phy_iac_cmd {
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MT7531_MDIO_ADDR = 0,
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MT7531_MDIO_WRITE = 1,
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MT7531_MDIO_READ = 2,
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MT7531_MDIO_READ_CL45 = 3,
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};
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/* MDIO_ST: MDIO start field */
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enum mt7531_mdio_st {
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MT7531_MDIO_ST_CL45 = 0,
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MT7531_MDIO_ST_CL22 = 1,
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};
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#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
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MT7531_MDIO_CMD(MT7531_MDIO_READ))
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#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
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MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
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#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
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MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
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#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
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MT7531_MDIO_CMD(MT7531_MDIO_READ))
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#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
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MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
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/* Register for RGMII clock phase */
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#define MT7531_CLKGEN_CTRL 0x7500
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#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
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#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
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#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
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#define CLK_SKEW_IN_MASK GENMASK(7, 6)
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#define RXCLK_NO_DELAY BIT(5)
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#define TXCLK_NO_REVERSE BIT(4)
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#define GP_MODE(x) (((x) & 0x3) << 1)
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#define GP_MODE_MASK GENMASK(2, 1)
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#define GP_CLK_EN BIT(0)
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enum mt7531_gp_mode {
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MT7531_GP_MODE_RGMII = 0,
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MT7531_GP_MODE_MII = 1,
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MT7531_GP_MODE_REV_MII = 2
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};
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enum mt7531_clk_skew {
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MT7531_CLK_SKEW_NO_CHG = 0,
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MT7531_CLK_SKEW_DLY_100PPS = 1,
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MT7531_CLK_SKEW_DLY_200PPS = 2,
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MT7531_CLK_SKEW_REVERSE = 3,
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};
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/* Register for hw trap status */
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#define MT7530_HWTRAP 0x7800
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#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
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@ -267,6 +425,16 @@ enum mt7530_vlan_port_attr {
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#define HWTRAP_XTAL_40MHZ (BIT(10))
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#define HWTRAP_XTAL_20MHZ (BIT(9))
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#define MT7531_HWTRAP 0x7800
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#define HWTRAP_XTAL_FSEL_MASK BIT(7)
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#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
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#define HWTRAP_XTAL_FSEL_40MHZ 0
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/* Unique fields of (M)HWSTRAP for MT7531 */
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#define XTAL_FSEL_S 7
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#define XTAL_FSEL_M BIT(7)
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#define PHY_EN BIT(6)
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#define CHG_STRAP BIT(8)
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/* Register for hw trap modification */
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#define MT7530_MHWTRAP 0x7804
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#define MHWTRAP_PHY0_SEL BIT(20)
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@ -281,14 +449,37 @@ enum mt7530_vlan_port_attr {
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#define MT7530_TOP_SIG_CTRL 0x7808
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#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
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#define MT7531_TOP_SIG_SR 0x780c
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#define PAD_DUAL_SGMII_EN BIT(1)
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#define PAD_MCM_SMI_EN BIT(0)
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#define MT7530_IO_DRV_CR 0x7810
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#define P5_IO_CLK_DRV(x) ((x) & 0x3)
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#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
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#define MT7531_CHIP_REV 0x781C
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#define MT7531_PLLGP_EN 0x7820
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#define EN_COREPLL BIT(2)
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#define SW_CLKSW BIT(1)
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#define SW_PLLGP BIT(0)
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#define MT7530_P6ECR 0x7830
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#define P6_INTF_MODE_MASK 0x3
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#define P6_INTF_MODE(x) ((x) & 0x3)
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#define MT7531_PLLGP_CR0 0x78a8
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#define RG_COREPLL_EN BIT(22)
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#define RG_COREPLL_POSDIV_S 23
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#define RG_COREPLL_POSDIV_M 0x3800000
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#define RG_COREPLL_SDM_PCW_S 1
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#define RG_COREPLL_SDM_PCW_M 0x3ffffe
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#define RG_COREPLL_SDM_PCW_CHG BIT(0)
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/* Registers for RGMII and SGMII PLL clock */
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#define MT7531_ANA_PLLGP_CR2 0x78b0
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#define MT7531_ANA_PLLGP_CR5 0x78bc
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/* Registers for TRGMII on the both side */
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#define MT7530_TRGMII_RCK_CTRL 0x7a00
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#define RX_RST BIT(31)
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@ -327,10 +518,25 @@ enum mt7530_vlan_port_attr {
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#define MT7530_P5RGMIITXCR 0x7b04
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#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
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/* Registers for GPIO mode */
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#define MT7531_GPIO_MODE0 0x7c0c
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#define MT7531_GPIO0_MASK GENMASK(3, 0)
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#define MT7531_GPIO0_INTERRUPT 1
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#define MT7531_GPIO_MODE1 0x7c10
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#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
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#define MT7531_EXT_P_MDC_11 (2 << 12)
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#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
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#define MT7531_EXT_P_MDIO_12 (2 << 16)
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#define MT7530_CREV 0x7ffc
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#define CHIP_NAME_SHIFT 16
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#define MT7530_ID 0x7530
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#define MT7531_CREV 0x781C
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#define CHIP_REV_M 0x0f
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#define MT7531_ID 0x7531
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/* Registers for core PLL access through mmd indirect */
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#define CORE_PLL_GROUP2 0x401
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#define RG_SYSPLL_EN_NORMAL BIT(15)
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@ -347,6 +553,10 @@ enum mt7530_vlan_port_attr {
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#define RG_SYSPLL_DDSFBK_EN BIT(12)
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#define RG_SYSPLL_BIAS_EN BIT(11)
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#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
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#define MT7531_PHY_PLL_OFF BIT(5)
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#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
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#define MT753X_CTRL_PHY_ADDR 0
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#define CORE_PLL_GROUP5 0x404
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#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
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@ -425,6 +635,7 @@ enum p5_interface_select {
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P5_INTF_SEL_PHY_P0,
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P5_INTF_SEL_PHY_P4,
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P5_INTF_SEL_GMAC5,
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P5_INTF_SEL_GMAC5_SGMII,
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};
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static const char *p5_intf_modes(unsigned int p5_interface)
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@ -438,6 +649,8 @@ static const char *p5_intf_modes(unsigned int p5_interface)
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return "PHY P4";
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case P5_INTF_SEL_GMAC5:
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return "GMAC5";
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case P5_INTF_SEL_GMAC5_SGMII:
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return "GMAC5_SGMII";
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default:
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return "unknown";
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}
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@ -458,6 +671,10 @@ static const char *p5_intf_modes(unsigned int p5_interface)
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* MAC port
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* @mac_port_config: Holding the way setting up the PHY attribute to a
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* certain MAC port
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* @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
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* certain MAC port
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* @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
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* of the certain MAC port
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*/
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struct mt753x_info {
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enum mt753x_id id;
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@ -466,6 +683,7 @@ struct mt753x_info {
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int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
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int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
|
||||
int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
|
||||
int (*cpu_port_config)(struct dsa_switch *ds, int port);
|
||||
bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
|
||||
const struct phylink_link_state *state);
|
||||
void (*mac_port_validate)(struct dsa_switch *ds, int port,
|
||||
@ -475,6 +693,10 @@ struct mt753x_info {
|
||||
int (*mac_port_config)(struct dsa_switch *ds, int port,
|
||||
unsigned int mode,
|
||||
phy_interface_t interface);
|
||||
void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
|
||||
void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
|
||||
unsigned int mode, phy_interface_t interface,
|
||||
int speed, int duplex);
|
||||
};
|
||||
|
||||
/* struct mt7530_priv - This is the main data structure for holding the state
|
||||
|
||||
Loading…
Reference in New Issue
Block a user