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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'stmmac-next'
Jose Abreu says: ==================== net: stmmac: Improvements for -next Misc improvements for stmmac. Patch 1/6, fixes a sparse warning that was introduced in recent commit in -next. Patch 2/6, adds the Split Header support which is also available in XGMAC cores and now in GMAC4+ with this patch. Patch 3/6, adds the C45 support for MDIO transactions when using XGMAC cores. Patch 4/6, removes the speed dependency on CBS callbacks so that it can be used in XGMAC cores. Patch 5/6, reworks the over-engineered stmmac_rx() function so that its easier to read. Patch 6/6, implements the UDP Segmentation Offload feature in GMAC4+ cores. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
ca22d6977b
@ -14,6 +14,7 @@
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/* MAC registers */
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#define GMAC_CONFIG 0x00000000
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#define GMAC_EXT_CONFIG 0x00000004
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#define GMAC_PACKET_FILTER 0x00000008
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#define GMAC_HASH_TAB(x) (0x10 + (x) * 4)
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#define GMAC_VLAN_TAG 0x00000050
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@ -188,6 +189,11 @@ enum power_event {
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#define GMAC_CONFIG_TE BIT(1)
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#define GMAC_CONFIG_RE BIT(0)
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/* MAC extended config */
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#define GMAC_CONFIG_HDSMS GENMASK(22, 20)
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#define GMAC_CONFIG_HDSMS_SHIFT 20
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#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
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/* MAC HW features0 bitmap */
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#define GMAC_HW_FEAT_SAVLANINS BIT(27)
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#define GMAC_HW_FEAT_ADDMAC BIT(18)
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@ -211,6 +217,7 @@ enum power_event {
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#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
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#define GMAC_HW_FEAT_AVSEL BIT(20)
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#define GMAC_HW_TSOEN BIT(18)
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#define GMAC_HW_FEAT_SPHEN BIT(17)
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#define GMAC_HW_ADDR64 GENMASK(15, 14)
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#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
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#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
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@ -733,7 +733,7 @@ static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
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}
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static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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u16 perfect_match, bool is_double)
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__le16 perfect_match, bool is_double)
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{
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void __iomem *ioaddr = hw->pcsr;
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@ -83,9 +83,10 @@ static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
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if (unlikely(rdes3 & RDES3_OWN))
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return dma_own;
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/* Verify rx error by looking at the last segment. */
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if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
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if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
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return discard_frame;
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if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
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return rx_not_ls;
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if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
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if (unlikely(rdes3 & RDES3_GIANT_PACKET))
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@ -188,7 +189,7 @@ static void dwmac4_set_tx_owner(struct dma_desc *p)
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static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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{
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p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
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p->des3 |= cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
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if (!disable_rx_ic)
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p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
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@ -492,6 +493,18 @@ static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
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p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
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}
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static int dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
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{
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*len = le32_to_cpu(p->des2) & RDES2_HL;
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return 0;
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}
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static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr)
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{
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p->des2 = cpu_to_le32(lower_32_bits(addr));
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p->des3 = cpu_to_le32(upper_32_bits(addr) | RDES3_BUFFER2_VALID_ADDR);
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}
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const struct stmmac_desc_ops dwmac4_desc_ops = {
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.tx_status = dwmac4_wrback_get_tx_status,
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.rx_status = dwmac4_wrback_get_rx_status,
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@ -519,6 +532,8 @@ const struct stmmac_desc_ops dwmac4_desc_ops = {
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.set_sarc = dwmac4_set_sarc,
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.set_vlan_tag = dwmac4_set_vlan_tag,
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.set_vlan = dwmac4_set_vlan,
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.get_rx_header_len = dwmac4_get_rx_header_len,
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.set_sec_addr = dwmac4_set_sec_addr,
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};
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const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
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@ -109,6 +109,7 @@
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#define RDES2_L4_FILTER_MATCH BIT(28)
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#define RDES2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26)
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#define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26
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#define RDES2_HL GENMASK(9, 0)
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/* RDES3 (write back format) */
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#define RDES3_PACKET_SIZE_MASK GENMASK(14, 0)
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@ -368,6 +368,7 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
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dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
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dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
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dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
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dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
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dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
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switch (dma_cap->addr64) {
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@ -460,6 +461,22 @@ static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
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writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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}
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static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
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{
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u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
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value &= ~GMAC_CONFIG_HDSMS;
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value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
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writel(value, ioaddr + GMAC_EXT_CONFIG);
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value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
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if (en)
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value |= DMA_CONTROL_SPH;
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else
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value &= ~DMA_CONTROL_SPH;
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writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
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}
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const struct stmmac_dma_ops dwmac4_dma_ops = {
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.reset = dwmac4_dma_reset,
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.init = dwmac4_dma_init,
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@ -486,6 +503,7 @@ const struct stmmac_dma_ops dwmac4_dma_ops = {
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.enable_tso = dwmac4_enable_tso,
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.qmode = dwmac4_qmode,
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.set_bfsize = dwmac4_set_bfsize,
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.enable_sph = dwmac4_enable_sph,
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};
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const struct stmmac_dma_ops dwmac410_dma_ops = {
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@ -514,4 +532,5 @@ const struct stmmac_dma_ops dwmac410_dma_ops = {
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.enable_tso = dwmac4_enable_tso,
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.qmode = dwmac4_qmode,
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.set_bfsize = dwmac4_set_bfsize,
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.enable_sph = dwmac4_enable_sph,
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};
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@ -110,6 +110,7 @@
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#define DMA_CHAN_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x60)
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/* DMA Control X */
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#define DMA_CONTROL_SPH BIT(24)
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#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
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/* DMA Tx Channel X Control register defines */
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@ -556,7 +556,7 @@ static int dwxgmac2_rss_configure(struct mac_device_info *hw,
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}
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static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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u16 perfect_match, bool is_double)
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__le16 perfect_match, bool is_double)
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{
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void __iomem *ioaddr = hw->pcsr;
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@ -357,7 +357,7 @@ struct stmmac_ops {
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struct stmmac_rss *cfg, u32 num_rxq);
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/* VLAN */
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void (*update_vlan_hash)(struct mac_device_info *hw, u32 hash,
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u16 perfect_match, bool is_double);
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__le16 perfect_match, bool is_double);
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void (*enable_vlan)(struct mac_device_info *hw, u32 type);
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/* TX Timestamp */
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int (*get_mac_tx_timestamp)(struct mac_device_info *hw, u64 *ts);
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@ -36,6 +36,7 @@
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#endif /* CONFIG_DEBUG_FS */
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#include <linux/net_tstamp.h>
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#include <linux/phylink.h>
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#include <linux/udp.h>
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#include <net/pkt_cls.h>
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#include "stmmac_ptp.h"
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#include "stmmac.h"
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@ -2916,9 +2917,9 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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u32 queue = skb_get_queue_mapping(skb);
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struct stmmac_tx_queue *tx_q;
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unsigned int first_entry;
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u8 proto_hdr_len, hdr;
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int tmp_pay_len = 0;
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u32 pay_len, mss;
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u8 proto_hdr_len;
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dma_addr_t des;
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bool has_vlan;
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int i;
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@ -2926,7 +2927,13 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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tx_q = &priv->tx_queue[queue];
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/* Compute header lengths */
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proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
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if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
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proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
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hdr = sizeof(struct udphdr);
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} else {
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proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
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hdr = tcp_hdrlen(skb);
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}
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/* Desc availability based on threshold should be enough safe */
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if (unlikely(stmmac_tx_avail(priv, queue) <
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@ -2956,8 +2963,8 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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}
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if (netif_msg_tx_queued(priv)) {
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pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
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__func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
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pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
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__func__, hdr, proto_hdr_len, pay_len, mss);
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pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
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skb->data_len);
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}
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@ -3071,7 +3078,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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proto_hdr_len,
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pay_len,
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1, tx_q->tx_skbuff_dma[first_entry].last_segment,
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tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
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hdr / 4, (skb->len - proto_hdr_len));
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/* If context desc is used to change MSS */
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if (mss_desc) {
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@ -3130,6 +3137,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
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int i, csum_insertion = 0, is_jumbo = 0;
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u32 queue = skb_get_queue_mapping(skb);
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int nfrags = skb_shinfo(skb)->nr_frags;
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int gso = skb_shinfo(skb)->gso_type;
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struct dma_desc *desc, *first;
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struct stmmac_tx_queue *tx_q;
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unsigned int first_entry;
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@ -3145,7 +3153,9 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
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/* Manage oversized TCP frames for GMAC4 device */
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if (skb_is_gso(skb) && priv->tso) {
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if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
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if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
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return stmmac_tso_xmit(skb, dev);
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if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
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return stmmac_tso_xmit(skb, dev);
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}
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@ -3443,6 +3453,55 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
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stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
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}
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static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
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struct dma_desc *p,
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int status, unsigned int len)
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{
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int ret, coe = priv->hw->rx_csum;
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unsigned int plen = 0, hlen = 0;
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/* Not first descriptor, buffer is always zero */
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if (priv->sph && len)
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return 0;
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/* First descriptor, get split header length */
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ret = stmmac_get_rx_header_len(priv, p, &hlen);
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if (priv->sph && hlen) {
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priv->xstats.rx_split_hdr_pkt_n++;
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return hlen;
|
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}
|
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/* First descriptor, not last descriptor and not split header */
|
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if (status & rx_not_ls)
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return priv->dma_buf_sz;
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plen = stmmac_get_rx_frame_len(priv, p, coe);
|
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|
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/* First descriptor and last descriptor and not split header */
|
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return min_t(unsigned int, priv->dma_buf_sz, plen);
|
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}
|
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|
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static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
|
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struct dma_desc *p,
|
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int status, unsigned int len)
|
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{
|
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int coe = priv->hw->rx_csum;
|
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unsigned int plen = 0;
|
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|
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/* Not split header, buffer is not available */
|
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if (!priv->sph)
|
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return 0;
|
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|
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/* Not last descriptor */
|
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if (status & rx_not_ls)
|
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return priv->dma_buf_sz;
|
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|
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plen = stmmac_get_rx_frame_len(priv, p, coe);
|
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|
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/* Last descriptor */
|
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return plen - len;
|
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}
|
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|
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/**
|
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* stmmac_rx - manage the receive process
|
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* @priv: driver private structure
|
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@ -3472,11 +3531,10 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
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stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
|
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}
|
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while (count < limit) {
|
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unsigned int hlen = 0, prev_len = 0;
|
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unsigned int buf1_len = 0, buf2_len = 0;
|
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enum pkt_hash_types hash_type;
|
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struct stmmac_rx_buffer *buf;
|
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struct dma_desc *np, *p;
|
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unsigned int sec_len;
|
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int entry;
|
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u32 hash;
|
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|
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@ -3495,7 +3553,8 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
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break;
|
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|
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read_again:
|
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sec_len = 0;
|
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buf1_len = 0;
|
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buf2_len = 0;
|
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entry = next_entry;
|
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buf = &rx_q->buf_pool[entry];
|
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|
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@ -3520,7 +3579,6 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
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np = rx_q->dma_rx + next_entry;
|
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|
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prefetch(np);
|
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prefetch(page_address(buf->page));
|
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|
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if (priv->extend_desc)
|
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stmmac_rx_extended_status(priv, &priv->dev->stats,
|
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@ -3537,69 +3595,61 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
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goto read_again;
|
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if (unlikely(error)) {
|
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dev_kfree_skb(skb);
|
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skb = NULL;
|
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count++;
|
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continue;
|
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}
|
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|
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/* Buffer is good. Go on. */
|
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|
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if (likely(status & rx_not_ls)) {
|
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len += priv->dma_buf_sz;
|
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} else {
|
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prev_len = len;
|
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len = stmmac_get_rx_frame_len(priv, p, coe);
|
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prefetch(page_address(buf->page));
|
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if (buf->sec_page)
|
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prefetch(page_address(buf->sec_page));
|
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|
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/* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
|
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* Type frames (LLC/LLC-SNAP)
|
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*
|
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* llc_snap is never checked in GMAC >= 4, so this ACS
|
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* feature is always disabled and packets need to be
|
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* stripped manually.
|
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*/
|
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if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
|
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unlikely(status != llc_snap))
|
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len -= ETH_FCS_LEN;
|
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buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
|
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len += buf1_len;
|
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buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
|
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len += buf2_len;
|
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|
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/* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
|
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* Type frames (LLC/LLC-SNAP)
|
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*
|
||||
* llc_snap is never checked in GMAC >= 4, so this ACS
|
||||
* feature is always disabled and packets need to be
|
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* stripped manually.
|
||||
*/
|
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if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
|
||||
unlikely(status != llc_snap)) {
|
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if (buf2_len)
|
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buf2_len -= ETH_FCS_LEN;
|
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else
|
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buf1_len -= ETH_FCS_LEN;
|
||||
|
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len -= ETH_FCS_LEN;
|
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}
|
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|
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if (!skb) {
|
||||
int ret = stmmac_get_rx_header_len(priv, p, &hlen);
|
||||
|
||||
if (priv->sph && !ret && (hlen > 0)) {
|
||||
sec_len = len;
|
||||
if (!(status & rx_not_ls))
|
||||
sec_len = sec_len - hlen;
|
||||
len = hlen;
|
||||
|
||||
prefetch(page_address(buf->sec_page));
|
||||
priv->xstats.rx_split_hdr_pkt_n++;
|
||||
}
|
||||
|
||||
skb = napi_alloc_skb(&ch->rx_napi, len);
|
||||
skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
|
||||
if (!skb) {
|
||||
priv->dev->stats.rx_dropped++;
|
||||
count++;
|
||||
continue;
|
||||
goto drain_data;
|
||||
}
|
||||
|
||||
dma_sync_single_for_cpu(priv->device, buf->addr, len,
|
||||
DMA_FROM_DEVICE);
|
||||
dma_sync_single_for_cpu(priv->device, buf->addr,
|
||||
buf1_len, DMA_FROM_DEVICE);
|
||||
skb_copy_to_linear_data(skb, page_address(buf->page),
|
||||
len);
|
||||
skb_put(skb, len);
|
||||
buf1_len);
|
||||
skb_put(skb, buf1_len);
|
||||
|
||||
/* Data payload copied into SKB, page ready for recycle */
|
||||
page_pool_recycle_direct(rx_q->page_pool, buf->page);
|
||||
buf->page = NULL;
|
||||
} else {
|
||||
unsigned int buf_len = len - prev_len;
|
||||
|
||||
if (likely(status & rx_not_ls))
|
||||
buf_len = priv->dma_buf_sz;
|
||||
|
||||
} else if (buf1_len) {
|
||||
dma_sync_single_for_cpu(priv->device, buf->addr,
|
||||
buf_len, DMA_FROM_DEVICE);
|
||||
buf1_len, DMA_FROM_DEVICE);
|
||||
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
|
||||
buf->page, 0, buf_len,
|
||||
buf->page, 0, buf1_len,
|
||||
priv->dma_buf_sz);
|
||||
|
||||
/* Data payload appended into SKB */
|
||||
@ -3607,22 +3657,23 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
buf->page = NULL;
|
||||
}
|
||||
|
||||
if (sec_len > 0) {
|
||||
if (buf2_len) {
|
||||
dma_sync_single_for_cpu(priv->device, buf->sec_addr,
|
||||
sec_len, DMA_FROM_DEVICE);
|
||||
buf2_len, DMA_FROM_DEVICE);
|
||||
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
|
||||
buf->sec_page, 0, sec_len,
|
||||
buf->sec_page, 0, buf2_len,
|
||||
priv->dma_buf_sz);
|
||||
|
||||
len += sec_len;
|
||||
|
||||
/* Data payload appended into SKB */
|
||||
page_pool_release_page(rx_q->page_pool, buf->sec_page);
|
||||
buf->sec_page = NULL;
|
||||
}
|
||||
|
||||
drain_data:
|
||||
if (likely(status & rx_not_ls))
|
||||
goto read_again;
|
||||
if (!skb)
|
||||
continue;
|
||||
|
||||
/* Got entire packet into SKB. Finish it. */
|
||||
|
||||
@ -3640,13 +3691,14 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
|
||||
skb_record_rx_queue(skb, queue);
|
||||
napi_gro_receive(&ch->rx_napi, skb);
|
||||
skb = NULL;
|
||||
|
||||
priv->dev->stats.rx_packets++;
|
||||
priv->dev->stats.rx_bytes += len;
|
||||
count++;
|
||||
}
|
||||
|
||||
if (status & rx_not_ls) {
|
||||
if (status & rx_not_ls || skb) {
|
||||
rx_q->state_saved = true;
|
||||
rx_q->state.skb = skb;
|
||||
rx_q->state.error = error;
|
||||
@ -3994,11 +4046,13 @@ static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
||||
static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
|
||||
struct net_device *sb_dev)
|
||||
{
|
||||
if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
|
||||
int gso = skb_shinfo(skb)->gso_type;
|
||||
|
||||
if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
|
||||
/*
|
||||
* There is no way to determine the number of TSO
|
||||
* There is no way to determine the number of TSO/USO
|
||||
* capable Queues. Let's use always the Queue 0
|
||||
* because if TSO is supported then at least this
|
||||
* because if TSO/USO is supported then at least this
|
||||
* one will be capable.
|
||||
*/
|
||||
return 0;
|
||||
@ -4214,6 +4268,7 @@ static u32 stmmac_vid_crc32_le(__le16 vid_le)
|
||||
static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
|
||||
{
|
||||
u32 crc, hash = 0;
|
||||
__le16 pmatch = 0;
|
||||
int count = 0;
|
||||
u16 vid = 0;
|
||||
|
||||
@ -4228,11 +4283,11 @@ static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
|
||||
if (count > 2) /* VID = 0 always passes filter */
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
vid = cpu_to_le16(vid);
|
||||
pmatch = cpu_to_le16(vid);
|
||||
hash = 0;
|
||||
}
|
||||
|
||||
return stmmac_update_vlan_hash(priv, priv->hw, hash, vid, is_double);
|
||||
return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
|
||||
}
|
||||
|
||||
static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
|
||||
@ -4512,6 +4567,8 @@ int stmmac_dvr_probe(struct device *device,
|
||||
|
||||
if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
|
||||
ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
|
||||
if (priv->plat->has_gmac4)
|
||||
ndev->hw_features |= NETIF_F_GSO_UDP_L4;
|
||||
priv->tso = true;
|
||||
dev_info(priv->device, "TSO feature enabled\n");
|
||||
}
|
||||
|
||||
@ -41,20 +41,32 @@
|
||||
#define MII_XGMAC_BUSY BIT(22)
|
||||
#define MII_XGMAC_MAX_C22ADDR 3
|
||||
#define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
|
||||
#define MII_XGMAC_PA_SHIFT 16
|
||||
#define MII_XGMAC_DA_SHIFT 21
|
||||
|
||||
static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
|
||||
int phyreg, u32 *hw_addr)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* Set port as Clause 45 */
|
||||
tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
|
||||
tmp &= ~BIT(phyaddr);
|
||||
writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
|
||||
|
||||
*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
|
||||
*hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
|
||||
int phyreg, u32 *hw_addr)
|
||||
{
|
||||
unsigned int mii_data = priv->hw->mii.data;
|
||||
u32 tmp;
|
||||
|
||||
/* HW does not support C22 addr >= 4 */
|
||||
if (phyaddr > MII_XGMAC_MAX_C22ADDR)
|
||||
return -ENODEV;
|
||||
/* Wait until any existing MII operation is complete */
|
||||
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
|
||||
!(tmp & MII_XGMAC_BUSY), 100, 10000))
|
||||
return -EBUSY;
|
||||
|
||||
/* Set port as Clause 22 */
|
||||
tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
|
||||
@ -62,7 +74,7 @@ static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
|
||||
tmp |= BIT(phyaddr);
|
||||
writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
|
||||
|
||||
*hw_addr = (phyaddr << 16) | (phyreg & 0x1f);
|
||||
*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -75,17 +87,28 @@ static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
|
||||
u32 tmp, addr, value = MII_XGMAC_BUSY;
|
||||
int ret;
|
||||
|
||||
/* Wait until any existing MII operation is complete */
|
||||
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
|
||||
!(tmp & MII_XGMAC_BUSY), 100, 10000))
|
||||
return -EBUSY;
|
||||
|
||||
if (phyreg & MII_ADDR_C45) {
|
||||
return -EOPNOTSUPP;
|
||||
phyreg &= ~MII_ADDR_C45;
|
||||
|
||||
ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
value |= MII_XGMAC_SADDR;
|
||||
}
|
||||
|
||||
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
|
||||
& priv->hw->mii.clk_csr_mask;
|
||||
value |= MII_XGMAC_SADDR | MII_XGMAC_READ;
|
||||
value |= MII_XGMAC_READ;
|
||||
|
||||
/* Wait until any existing MII operation is complete */
|
||||
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
|
||||
@ -115,17 +138,28 @@ static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
|
||||
u32 addr, tmp, value = MII_XGMAC_BUSY;
|
||||
int ret;
|
||||
|
||||
/* Wait until any existing MII operation is complete */
|
||||
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
|
||||
!(tmp & MII_XGMAC_BUSY), 100, 10000))
|
||||
return -EBUSY;
|
||||
|
||||
if (phyreg & MII_ADDR_C45) {
|
||||
return -EOPNOTSUPP;
|
||||
phyreg &= ~MII_ADDR_C45;
|
||||
|
||||
ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
value |= MII_XGMAC_SADDR;
|
||||
}
|
||||
|
||||
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
|
||||
& priv->hw->mii.clk_csr_mask;
|
||||
value |= phydata | MII_XGMAC_SADDR;
|
||||
value |= phydata;
|
||||
value |= MII_XGMAC_WRITE;
|
||||
|
||||
/* Wait until any existing MII operation is complete */
|
||||
@ -363,6 +397,10 @@ int stmmac_mdio_register(struct net_device *ndev)
|
||||
goto bus_register_fail;
|
||||
}
|
||||
|
||||
/* Looks like we need a dummy read for XGMAC only and C45 PHYs */
|
||||
if (priv->plat->has_xgmac)
|
||||
stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);
|
||||
|
||||
if (priv->plat->phy_node || mdio_node)
|
||||
goto bus_register_done;
|
||||
|
||||
|
||||
@ -321,8 +321,6 @@ static int tc_setup_cbs(struct stmmac_priv *priv,
|
||||
return -EINVAL;
|
||||
if (!priv->dma_cap.av)
|
||||
return -EOPNOTSUPP;
|
||||
if (priv->speed != SPEED_100 && priv->speed != SPEED_1000)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
|
||||
if (mode_to_use == MTL_QUEUE_DCB && qopt->enable) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user