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PCI/ACPI: Rename _HPX structs from hpp_* to hpx_*
The names of the hpp_type0, hpp_type1 and hpp_type2 structs suggest that they're related to _HPP, when in fact they're related to _HPX. The struct hpp_type0 denotes an _HPX Type 0 setting record that supersedes the _HPP setting record, and it has been used interchangeably for _HPP as per the ACPI specification (see version 6.3, section 6.2.9.1) which states that it should be applied to PCI, PCI-X and PCI Express devices, with settings being ignored if they are not applicable. Rename them to hpx_type0, hpx_type1 and hpx_type2 to reflect their relation to _HPX rather than _HPP. Link: https://lore.kernel.org/r/20190827094951.10613-2-kw@linux.com Signed-off-by: Krzysztof Wilczynski <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Krzysztof Wilczynski
Bjorn Helgaas
parent
5f9e832c13
commit
e2797ad31f
@ -119,7 +119,7 @@ phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
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}
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static acpi_status decode_type0_hpx_record(union acpi_object *record,
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struct hpp_type0 *hpx0)
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struct hpx_type0 *hpx0)
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{
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int i;
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union acpi_object *fields = record->package.elements;
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@ -147,7 +147,7 @@ static acpi_status decode_type0_hpx_record(union acpi_object *record,
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}
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static acpi_status decode_type1_hpx_record(union acpi_object *record,
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struct hpp_type1 *hpx1)
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struct hpx_type1 *hpx1)
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{
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int i;
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union acpi_object *fields = record->package.elements;
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@ -174,7 +174,7 @@ static acpi_status decode_type1_hpx_record(union acpi_object *record,
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}
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static acpi_status decode_type2_hpx_record(union acpi_object *record,
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struct hpp_type2 *hpx2)
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struct hpx_type2 *hpx2)
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{
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int i;
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union acpi_object *fields = record->package.elements;
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@ -277,9 +277,9 @@ static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle,
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acpi_status status;
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struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
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union acpi_object *package, *record, *fields;
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struct hpp_type0 hpx0;
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struct hpp_type1 hpx1;
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struct hpp_type2 hpx2;
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struct hpx_type0 hpx0;
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struct hpx_type1 hpx1;
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struct hpx_type2 hpx2;
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u32 type;
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int i;
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@ -353,10 +353,10 @@ static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle,
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acpi_status status;
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struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
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union acpi_object *package, *fields;
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struct hpp_type0 hpp0;
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struct hpx_type0 hpx0;
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int i;
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memset(&hpp0, 0, sizeof(hpp0));
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memset(&hpx0, 0, sizeof(hpx0));
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status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer);
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if (ACPI_FAILURE(status))
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@ -377,13 +377,13 @@ static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle,
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}
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}
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hpp0.revision = 1;
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hpp0.cache_line_size = fields[0].integer.value;
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hpp0.latency_timer = fields[1].integer.value;
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hpp0.enable_serr = fields[2].integer.value;
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hpp0.enable_perr = fields[3].integer.value;
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hpx0.revision = 1;
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hpx0.cache_line_size = fields[0].integer.value;
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hpx0.latency_timer = fields[1].integer.value;
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hpx0.enable_serr = fields[2].integer.value;
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hpx0.enable_perr = fields[3].integer.value;
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hp_ops->program_type0(dev, &hpp0);
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hp_ops->program_type0(dev, &hpx0);
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exit:
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kfree(buffer.pointer);
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@ -1920,7 +1920,7 @@ static void pci_configure_mps(struct pci_dev *dev)
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p_mps, mps, mpss);
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}
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static struct hpp_type0 pci_default_type0 = {
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static struct hpx_type0 pci_default_type0 = {
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.revision = 1,
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.cache_line_size = 8,
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.latency_timer = 0x40,
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@ -1928,44 +1928,44 @@ static struct hpp_type0 pci_default_type0 = {
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.enable_perr = 0,
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};
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static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
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static void program_hpx_type0(struct pci_dev *dev, struct hpx_type0 *hpx)
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{
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u16 pci_cmd, pci_bctl;
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if (!hpp)
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hpp = &pci_default_type0;
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if (!hpx)
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hpx = &pci_default_type0;
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if (hpp->revision > 1) {
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if (hpx->revision > 1) {
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pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
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hpp->revision);
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hpp = &pci_default_type0;
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hpx->revision);
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hpx = &pci_default_type0;
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}
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer);
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pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
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if (hpp->enable_serr)
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if (hpx->enable_serr)
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pci_cmd |= PCI_COMMAND_SERR;
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if (hpp->enable_perr)
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if (hpx->enable_perr)
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pci_cmd |= PCI_COMMAND_PARITY;
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pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
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/* Program bridge control value */
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
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hpp->latency_timer);
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hpx->latency_timer);
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
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if (hpp->enable_perr)
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if (hpx->enable_perr)
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pci_bctl |= PCI_BRIDGE_CTL_PARITY;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
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}
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}
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static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
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static void program_hpx_type1(struct pci_dev *dev, struct hpx_type1 *hpx)
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{
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int pos;
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if (!hpp)
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if (!hpx)
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return;
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pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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@ -1990,20 +1990,20 @@ static bool pcie_root_rcb_set(struct pci_dev *dev)
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return false;
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}
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static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx)
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{
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int pos;
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u32 reg32;
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if (!hpp)
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if (!hpx)
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return;
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if (!pci_is_pcie(dev))
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return;
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if (hpp->revision > 1) {
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if (hpx->revision > 1) {
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pci_warn(dev, "PCIe settings rev %d not supported\n",
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hpp->revision);
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hpx->revision);
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return;
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}
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@ -2012,14 +2012,14 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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* those to make sure they're consistent with the rest of the
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* platform.
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*/
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hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
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hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
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PCI_EXP_DEVCTL_READRQ;
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hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
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hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
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PCI_EXP_DEVCTL_READRQ);
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/* Initialize Device Control Register */
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pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
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~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
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~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or);
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/* Initialize Link Control Register */
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if (pcie_cap_has_lnkctl(dev)) {
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@ -2028,13 +2028,13 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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* If the Root Port supports Read Completion Boundary of
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* 128, set RCB to 128. Otherwise, clear it.
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*/
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hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
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hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
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hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
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hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
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if (pcie_root_rcb_set(dev))
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hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
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hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
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pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
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~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
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~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or);
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}
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/* Find Advanced Error Reporting Enhanced Capability */
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@ -2044,22 +2044,22 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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/* Initialize Uncorrectable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
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reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
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reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
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/* Initialize Uncorrectable Error Severity Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
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reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
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reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
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/* Initialize Correctable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
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reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
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reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
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/* Initialize Advanced Error Capabilities and Control Register */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
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reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or;
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/* Don't enable ECRC generation or checking if unsupported */
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if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
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@ -2178,15 +2178,15 @@ static void program_hpx_type3_register(struct pci_dev *dev,
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pos, orig_value, write_reg);
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}
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static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx3)
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static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx)
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{
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if (!hpx3)
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if (!hpx)
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return;
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if (!pci_is_pcie(dev))
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return;
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program_hpx_type3_register(dev, hpx3);
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program_hpx_type3_register(dev, hpx);
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}
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
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@ -2370,9 +2370,9 @@ static void pci_configure_serr(struct pci_dev *dev)
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static void pci_configure_device(struct pci_dev *dev)
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{
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static const struct hotplug_program_ops hp_ops = {
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.program_type0 = program_hpp_type0,
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.program_type1 = program_hpp_type1,
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.program_type2 = program_hpp_type2,
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.program_type0 = program_hpx_type0,
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.program_type1 = program_hpx_type1,
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.program_type2 = program_hpx_type2,
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.program_type3 = program_hpx_type3,
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};
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@ -86,25 +86,25 @@ void pci_hp_deregister(struct hotplug_slot *slot);
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#define pci_hp_initialize(slot, bus, nr, name) \
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__pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME)
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/* PCI Setting Record (Type 0) */
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struct hpp_type0 {
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u32 revision;
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u8 cache_line_size;
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u8 latency_timer;
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/* _HPX PCI Setting Record (Type 0); same as _HPP */
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struct hpx_type0 {
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u32 revision; /* Not present in _HPP */
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u8 cache_line_size; /* Not applicable to PCIe */
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u8 latency_timer; /* Not applicable to PCIe */
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u8 enable_serr;
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u8 enable_perr;
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};
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/* PCI-X Setting Record (Type 1) */
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struct hpp_type1 {
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/* _HPX PCI-X Setting Record (Type 1) */
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struct hpx_type1 {
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u32 revision;
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u8 max_mem_read;
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u8 avg_max_split;
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u16 tot_max_split;
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};
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/* PCI Express Setting Record (Type 2) */
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struct hpp_type2 {
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/* _HPX PCI Express Setting Record (Type 2) */
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struct hpx_type2 {
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u32 revision;
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u32 unc_err_mask_and;
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u32 unc_err_mask_or;
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@ -124,9 +124,7 @@ struct hpp_type2 {
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u32 sec_unc_err_mask_or;
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};
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/*
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* _HPX PCI Express Setting Record (Type 3)
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*/
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/* _HPX PCI Express Setting Record (Type 3) */
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struct hpx_type3 {
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u16 device_type;
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u16 function_type;
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@ -145,10 +143,10 @@ struct hpx_type3 {
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};
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struct hotplug_program_ops {
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void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp);
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void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp);
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void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp);
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void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp);
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void (*program_type0)(struct pci_dev *dev, struct hpx_type0 *hpx);
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void (*program_type1)(struct pci_dev *dev, struct hpx_type1 *hpx);
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void (*program_type2)(struct pci_dev *dev, struct hpx_type2 *hpx);
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void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpx);
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};
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enum hpx_type3_dev_type {
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