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perf/marvell_cn10k: Fix TAD PMU register offset

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The existing offset of TAD_PRF and TAD_PFC registers are incorrect.
Hence, fix with the right register offsets.

Also, drop read of TAD_PRF register in tad_pmu_event_counter_start()
since we don't have to preserve any bit fields and always write
an updated value.

Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
Link: https://lore.kernel.org/r/20220614171356.773967-1-tanmay@marvell.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Tanmay Jagdale 2022-06-14 17:13:56 +00:00 committed by Will Deacon
parent 8e28e53f13
commit f5ebeb138f
1 changed files with 3 additions and 5 deletions
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8
drivers/perf/marvell_cn10k_tad_pmu.c
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@ -14,9 +14,9 @@
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#define TAD_PFC_OFFSET 0x0
#define TAD_PFC_OFFSET 0x800
#define TAD_PFC(counter) (TAD_PFC_OFFSET | (counter << 3))
#define TAD_PRF_OFFSET 0x100
#define TAD_PRF_OFFSET 0x900
#define TAD_PRF(counter) (TAD_PRF_OFFSET | (counter << 3))
#define TAD_PRF_CNTSEL_MASK 0xFF
#define TAD_MAX_COUNTERS 8
@ -96,9 +96,7 @@ static void tad_pmu_event_counter_start(struct perf_event *event, int flags)
* which sets TAD()_PRF()[CNTSEL] != 0
*/
for (i = 0; i < tad_pmu->region_cnt; i++) {
reg_val = readq_relaxed(tad_pmu->regions[i].base +
TAD_PRF(counter_idx));
reg_val |= (event_idx & 0xFF);
reg_val = event_idx & 0xFF;
writeq_relaxed(reg_val, tad_pmu->regions[i].base +
TAD_PRF(counter_idx));
}