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pwm: rockchip: Added to support for RK3288 SoC

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This patch added to support the PWM controller found on
RK3288 SoC.

Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Caesar Wang 2014-08-08 15:28:49 +08:00 committed by Thierry Reding
parent 695d49d941
commit f630629908
1 changed files with 111 additions and 24 deletions
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135
drivers/pwm/pwm-rockchip.c
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@ -2,6 +2,7 @@
* PWM driver for Rockchip SoCs * PWM driver for Rockchip SoCs
* *
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
* Copyright (C) 2014 ROCKCHIP, Inc.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
@ -12,30 +13,81 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pwm.h> #include <linux/pwm.h>
#include <linux/time.h> #include <linux/time.h>
#define PWM_CNTR 0x00 /* Counter register */
#define PWM_HRC 0x04 /* High reference register */
#define PWM_LRC 0x08 /* Low reference register */
#define PWM_CTRL 0x0c /* Control register */
#define PWM_CTRL_TIMER_EN (1 << 0) #define PWM_CTRL_TIMER_EN (1 << 0)
#define PWM_CTRL_OUTPUT_EN (1 << 3) #define PWM_CTRL_OUTPUT_EN (1 << 3)
#define PRESCALER 2 #define PWM_ENABLE (1 << 0)
#define PWM_CONTINUOUS (1 << 1)
#define PWM_DUTY_POSITIVE (1 << 3)
#define PWM_INACTIVE_NEGATIVE (0 << 4)
#define PWM_OUTPUT_LEFT (0 << 5)
#define PWM_LP_DISABLE (0 << 8)
struct rockchip_pwm_chip { struct rockchip_pwm_chip {
struct pwm_chip chip; struct pwm_chip chip;
struct clk *clk; struct clk *clk;
const struct rockchip_pwm_data *data;
void __iomem *base; void __iomem *base;
}; };
struct rockchip_pwm_regs {
unsigned long duty;
unsigned long period;
unsigned long cntr;
unsigned long ctrl;
};
struct rockchip_pwm_data {
struct rockchip_pwm_regs regs;
unsigned int prescaler;
void (*set_enable)(struct pwm_chip *chip, bool enable);
};
static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
{ {
return container_of(c, struct rockchip_pwm_chip, chip); return container_of(c, struct rockchip_pwm_chip, chip);
} }
static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
u32 val;
val = readl_relaxed(pc->base + pc->data->regs.ctrl);
if (enable)
val |= enable_conf;
else
val &= ~enable_conf;
writel_relaxed(val, pc->base + pc->data->regs.ctrl);
}
static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
PWM_CONTINUOUS | PWM_DUTY_POSITIVE |
PWM_INACTIVE_NEGATIVE;
u32 val;
val = readl_relaxed(pc->base + pc->data->regs.ctrl);
if (enable)
val |= enable_conf;
else
val &= ~enable_conf;
writel_relaxed(val, pc->base + pc->data->regs.ctrl);
}
static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns) int duty_ns, int period_ns)
{ {
@ -52,20 +104,20 @@ static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* default prescaler value for all practical clock rate values. * default prescaler value for all practical clock rate values.
*/ */
div = clk_rate * period_ns; div = clk_rate * period_ns;
do_div(div, PRESCALER * NSEC_PER_SEC); do_div(div, pc->data->prescaler * NSEC_PER_SEC);
period = div; period = div;
div = clk_rate * duty_ns; div = clk_rate * duty_ns;
do_div(div, PRESCALER * NSEC_PER_SEC); do_div(div, pc->data->prescaler * NSEC_PER_SEC);
duty = div; duty = div;
ret = clk_enable(pc->clk); ret = clk_enable(pc->clk);
if (ret) if (ret)
return ret; return ret;
writel(period, pc->base + PWM_LRC); writel(period, pc->base + pc->data->regs.period);
writel(duty, pc->base + PWM_HRC); writel(duty, pc->base + pc->data->regs.duty);
writel(0, pc->base + PWM_CNTR); writel(0, pc->base + pc->data->regs.cntr);
clk_disable(pc->clk); clk_disable(pc->clk);
@ -76,15 +128,12 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{ {
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
int ret; int ret;
u32 val;
ret = clk_enable(pc->clk); ret = clk_enable(pc->clk);
if (ret) if (ret)
return ret; return ret;
val = readl_relaxed(pc->base + PWM_CTRL); pc->data->set_enable(chip, true);
val |= PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
writel_relaxed(val, pc->base + PWM_CTRL);
return 0; return 0;
} }
@ -92,11 +141,8 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{ {
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
u32 val;
val = readl_relaxed(pc->base + PWM_CTRL); pc->data->set_enable(chip, false);
val &= ~(PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN);
writel_relaxed(val, pc->base + PWM_CTRL);
clk_disable(pc->clk); clk_disable(pc->clk);
} }
@ -108,12 +154,58 @@ static const struct pwm_ops rockchip_pwm_ops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
}; };
static const struct rockchip_pwm_data pwm_data_v1 = {
.regs = {
.duty = 0x04,
.period = 0x08,
.cntr = 0x00,
.ctrl = 0x0c,
},
.prescaler = 2,
.set_enable = rockchip_pwm_set_enable_v1,
};
static const struct rockchip_pwm_data pwm_data_v2 = {
.regs = {
.duty = 0x08,
.period = 0x04,
.cntr = 0x00,
.ctrl = 0x0c,
},
.prescaler = 1,
.set_enable = rockchip_pwm_set_enable_v2,
};
static const struct rockchip_pwm_data pwm_data_vop = {
.regs = {
.duty = 0x08,
.period = 0x04,
.cntr = 0x0c,
.ctrl = 0x00,
},
.prescaler = 1,
.set_enable = rockchip_pwm_set_enable_v2,
};
static const struct of_device_id rockchip_pwm_dt_ids[] = {
{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
static int rockchip_pwm_probe(struct platform_device *pdev) static int rockchip_pwm_probe(struct platform_device *pdev)
{ {
const struct of_device_id *id;
struct rockchip_pwm_chip *pc; struct rockchip_pwm_chip *pc;
struct resource *r; struct resource *r;
int ret; int ret;
id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
if (!id)
return -EINVAL;
pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
if (!pc) if (!pc)
return -ENOMEM; return -ENOMEM;
@ -133,6 +225,7 @@ static int rockchip_pwm_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pc); platform_set_drvdata(pdev, pc);
pc->data = id->data;
pc->chip.dev = &pdev->dev; pc->chip.dev = &pdev->dev;
pc->chip.ops = &rockchip_pwm_ops; pc->chip.ops = &rockchip_pwm_ops;
pc->chip.base = -1; pc->chip.base = -1;
@ -156,12 +249,6 @@ static int rockchip_pwm_remove(struct platform_device *pdev)
return pwmchip_remove(&pc->chip); return pwmchip_remove(&pc->chip);
} }
static const struct of_device_id rockchip_pwm_dt_ids[] = {
{ .compatible = "rockchip,rk2928-pwm" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
static struct platform_driver rockchip_pwm_driver = { static struct platform_driver rockchip_pwm_driver = {
.driver = { .driver = {
.name = "rockchip-pwm", .name = "rockchip-pwm",