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ASoC: amd: fix spelling mistakes

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Fix some spelling mistakes as follows:
descritor ==> descriptor
descriptore ==> descriptor
contiguos ==> contiguous
initiailize ==> initialize
descriptiors ==> descriptor

Signed-off-by: Gu Shengxian <gushengxian@yulong.com>
Link: https://lore.kernel.org/r/20210706064207.672491-1-gushengxian507419@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Gu Shengxian 2021-07-05 23:42:07 -07:00 committed by Mark Brown
parent 3694f996be
commit f7c4fe9cff
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 7 additions and 7 deletions
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12
sound/soc/amd/acp-pcm-dma.c
View File

@ -156,7 +156,7 @@ static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
} }
/* Initialize a dma descriptor in SRAM based on descritor information passed */ /* Initialize a dma descriptor in SRAM based on descriptor information passed */
static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
u16 descr_idx, u16 descr_idx,
acp_dma_dscr_transfer_t *descr_info) acp_dma_dscr_transfer_t *descr_info)
@ -288,7 +288,7 @@ static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
&dmadscr[i]); &dmadscr[i]);
} }
pre_config_reset(acp_mmio, ch); pre_config_reset(acp_mmio, ch);
/* Configure the DMA channel with the above descriptore */ /* Configure the DMA channel with the above descriptor */
config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
NUM_DSCRS_PER_CHANNEL, NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL); ACP_DMA_PRIORITY_LEVEL_NORMAL);
@ -322,7 +322,7 @@ static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
high |= BIT(31); high |= BIT(31);
acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* Move to next physically contiguos page */ /* Move to next physically contiguous page */
addr += PAGE_SIZE; addr += PAGE_SIZE;
} }
} }
@ -602,11 +602,11 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type)
acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
} }
/* initiailize Onion control DAGB register */ /* initialize Onion control DAGB register */
acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
mmACP_AXI2DAGB_ONION_CNTL); mmACP_AXI2DAGB_ONION_CNTL);
/* initiailize Garlic control DAGB registers */ /* initialize Garlic control DAGB registers */
acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
mmACP_AXI2DAGB_GARLIC_CNTL); mmACP_AXI2DAGB_GARLIC_CNTL);
@ -621,7 +621,7 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type)
acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
mmACP_DMA_DESC_BASE_ADDR); mmACP_DMA_DESC_BASE_ADDR);
/* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ /* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */
acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
acp_mmio, mmACP_EXTERNAL_INTR_CNTL); acp_mmio, mmACP_EXTERNAL_INTR_CNTL);

2
sound/soc/amd/raven/acp3x-pcm-dma.c
View File

@ -147,7 +147,7 @@ static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
high |= BIT(31); high |= BIT(31);
rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
+ 4); + 4);
/* Move to next physically contiguos page */ /* Move to next physically contiguous page */
val += 8; val += 8;
addr += PAGE_SIZE; addr += PAGE_SIZE;
} }