6655 Commits

Author SHA1 Message Date
Bjorn Helgaas
fa687fb9ce Merge branch 'remotes/lorenzo/pci/vmd'
- Whitelist VMD devices with fast interrupt handlers to avoid sharing
    vectors with slow handlers (Keith Busch)

* remotes/lorenzo/pci/vmd:
  PCI: vmd: White list for fast interrupt handlers
2018-08-15 14:59:16 -05:00
Bjorn Helgaas
323fc7509a Merge branch 'remotes/lorenzo/pci/mvebu'
- Fix mvebu I/O space remapping issues (Thomas Petazzoni)

  - Use generic pci_host_bridge in mvebu instead of ARM-specific API
    (Thomas Petazzoni)

* remotes/lorenzo/pci/mvebu:
  PCI: mvebu: Drop bogus comment above mvebu_pcie_map_registers()
  PCI: mvebu: Convert to use pci_host_bridge directly
  PCI: mvebu: Use resource_size() to remap I/O space
  PCI: mvebu: Only remap I/O space if configured
  PCI: mvebu: Fix I/O space end address calculation
  PCI: mvebu: Remove redundant platform_set_drvdata() call
2018-08-15 14:59:15 -05:00
Bjorn Helgaas
732c47019d Merge branch 'remotes/lorenzo/pci/mobiveil'
- Fix mobiveil iomem/phys_addr_t type usage (Lorenzo Pieralisi)

  - Fix mobiveil missing include file (Lorenzo Pieralisi)

  - Add mobiveil Kconfig/Makefile support (Lorenzo Pieralisi)

* remotes/lorenzo/pci/mobiveil:
  PCI: mobiveil: Add Kconfig/Makefile entries
  PCI: mobiveil: Add missing ../pci.h include
  PCI: mobiveil: Fix struct mobiveil_pcie.pcie_reg_base address type
  PCI: mobiveil: Integer overflow in IB_WIN_SIZE
2018-08-15 14:59:14 -05:00
Bjorn Helgaas
0ea77d2b20 Merge branch 'remotes/lorenzo/pci/iproc'
- Add more devices to Broadcom PAXC quirk (Ray Jui)

  - Work around corrupted Broadcom PAXC config space to enable SMMU and
    GICv3 ITS (Ray Jui)

  - Disable MSI parsing to work around broken Broadcom PAXC logic in some
    devices (Ray Jui)

  - Hide unconfigured functions to work around a Broadcom PAXC defect (Ray
    Jui)

  - Lower iproc log level to reduce console output during boot (Ray Jui)

* remotes/lorenzo/pci/iproc:
  PCI: iproc: Reduce inbound/outbound mapping print level
  PCI: iproc: Reject unconfigured physical functions from PAXC
  PCI: iproc: Disable MSI parsing in certain PAXC blocks
  PCI: iproc: Fix up corrupted PAXC root complex config registers
  PCI: iproc: Activate PAXC bridge quirk for more devices
2018-08-15 14:59:13 -05:00
Bjorn Helgaas
1974704ead Merge branch 'remotes/lorenzo/pci/hv'
- Remove unnecessary GFP_ATOMIC from Hyper-V "new child" allocation
    (Jia-Ju Bai)

* remotes/lorenzo/pci/hv:
  PCI: hv: Replace GFP_ATOMIC with GFP_KERNEL in new_pcichild_device()
2018-08-15 14:59:12 -05:00
Bjorn Helgaas
0c38011aba Merge branch 'remotes/lorenzo/pci/dwc'
- Add Kirin MSI support (Xiaowei Song)

  - Drop unnecessary root_bus_nr setting from exynos, imx6, keystone,
    armada8k, artpec6, designware-plat, histb, qcom, spear13xx (Shawn Guo)

  - Move link notification settings from DesignWare core to individual
    drivers (Gustavo Pimentel)

  - Add endpoint library MSI-X interfaces (Gustavo Pimentel)

  - Correct signature of endpoint library IRQ interfaces (Gustavo Pimentel)

  - Add DesignWare endpoint library MSI-X callbacks (Gustavo Pimentel)

  - Add endpoint library MSI-X test support (Gustavo Pimentel)

* remotes/lorenzo/pci/dwc:
  PCI: endpoint: Add MSI set maximum restriction
  tools: PCI: Add MSI-X support
  pci_endpoint_test: Add 2 ioctl commands
  pci-epf-test/pci_endpoint_test: Add MSI-X support
  pci-epf-test/pci_endpoint_test: Use irq_type module parameter
  pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace
  PCI: dwc: Add legacy interrupt callback handler
  PCI: dwc: Rework MSI callbacks handler
  PCI: dwc: Add MSI-X callbacks handler
  PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures
  PCI: endpoint: Add MSI-X interfaces
  PCI: dwc: Fix EP link notification implementation
  PCI: spear13xx: Drop unnecessary root_bus_nr setting
  PCI: qcom: Drop unnecessary root_bus_nr setting
  PCI: histb: Drop unnecessary root_bus_nr setting
  PCI: designware-plat: Drop unnecessary root_bus_nr setting
  PCI: artpec6: Drop unnecessary root_bus_nr setting
  PCI: armada8k: Drop unnecessary root_bus_nr setting
  PCI: keystone: Drop unnecessary root_bus_nr setting
  PCI: imx6: Drop unnecessary root_bus_nr setting
  PCI: exynos: Drop unnecessary root_bus_nr setting
  PCI: kirin: Add MSI support
2018-08-15 14:59:11 -05:00
Bjorn Helgaas
37f0e311bc Merge branch 'remotes/lorenzo/pci/cadence'
- Correct the Cadence cdns_pcie_writel() signature (Alan Douglas)

  - Add Cadence support for optional generic PHYs (Alan Douglas)

  - Add Cadence power management ops (Alan Douglas)

  - Remove redundant variable from Cadence driver (Colin Ian King)

* remotes/lorenzo/pci/cadence:
  PCI: pcie-cadence-ep: Remove redundant variable mmc
  PCI: cadence: Add shutdown callback to host driver
  PCI: cadence: Add Power Management ops for host and EP
  dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
  PCI: cadence: Add generic PHY support to host and EP drivers
  PCI: cadence: Update cdns_pcie_writel() function signature
2018-08-15 14:59:10 -05:00
Bjorn Helgaas
ce342a1aa8 Merge branch 'remotes/lorenzo/pci/aardvark'
- Remove Aardvark outbound window configuration (Evan Wang)

  - Fix Aardvark bridge window sizing issue (Zachary Zhang)

  - Convert Aardvark to use pci_host_probe() to reduce code duplication
    (Thomas Petazzoni)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Convert to use pci_host_probe()
  PCI: aardvark: Size bridges before resources allocation
  PCI: aardvark: Remove PCIe outbound window configuration
  PCI: aardvark: Introduce an advk_pcie_valid_device() helper

# Conflicts:
#	drivers/pci/controller/pci-aardvark.c
2018-08-15 14:59:09 -05:00
Bjorn Helgaas
0d56768651 Merge branch 'remotes/lorenzo/pci/controller/misc'
- Remove Xilinx AXI-PCIe host bridge arch dependency (Palmer Dabbelt)

* remotes/lorenzo/pci/controller/misc:
  PCI/xilinx: Depend on OF instead of the ARCH
2018-08-15 14:59:07 -05:00
Bjorn Helgaas
3a48dc6fc2 Merge branch 'pci/virtualization'
- To avoid bus errors, enable PASID only if entire path supports End-End
    TLP prefixes (Sinan Kaya)

  - Unify slot and bus reset functions and remove hotplug knowledge from
    callers (Sinan Kaya)

  - Add Function-Level Reset quirks for Intel and Samsung NVMe devices to
    fix guest reboot issues (Alex Williamson)

  - Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller
    (Bjorn Helgaas)

* pci/virtualization:
  PCI: Add function 1 DMA alias quirk for Marvell 88SS9183
  PCI: Delay after FLR of Intel DC P3700 NVMe
  PCI: Disable Samsung SM961/PM961 NVMe before FLR
  PCI: Export pcie_has_flr()
  PCI: Rename pci_try_reset_bus() to pci_reset_bus()
  PCI: Deprecate pci_reset_bus() and pci_reset_slot() functions
  PCI: Unify try slot and bus reset API
  PCI: Hide pci_reset_bridge_secondary_bus() from drivers
  IB/hfi1: Use pci_try_reset_bus() for initiating PCI Secondary Bus Reset
  PCI: Handle error return from pci_reset_bridge_secondary_bus()
  PCI/IOV: Tidy pci_sriov_set_totalvfs()
  PCI: Enable PASID only if entire path supports End-End TLP prefixes

# Conflicts:
#	drivers/pci/hotplug/pciehp_hpc.c
2018-08-15 14:59:06 -05:00
Bjorn Helgaas
e7aaf90f9d Merge branch 'pci/switchtec'
- Add DMA alias quirk for Microsemi Switchtec NTB (Doug Meyer)

  - Expand documentation for pci_add_dma_alias() (Logan Gunthorpe)

* pci/switchtec:
  PCI: Expand documentation for pci_add_dma_alias()
  PCI: Add DMA alias quirk for Microsemi Switchtec NTB
  switchtec: Use generic PCI Vendor ID and Class Code

# Conflicts:
#	drivers/pci/quirks.c
2018-08-15 14:59:03 -05:00
Bjorn Helgaas
5fc054a544 Merge branch 'pci/resource'
- Clean up devm_of_pci_get_host_bridge_resources() resource allocation
    (Jan Kiszka)

  - Fixup resizable BARs after suspend/resume (Christian König)

  - Make "pci=earlydump" generic (Sinan Kaya)

  - Fix ROM BAR access routines to stay in bounds and check for signature
    correctly (Rex Zhu)

* pci/resource:
  PCI: Make pci_get_rom_size() static
  PCI: Add check code for last image indicator not set
  PCI: Avoid accessing memory outside the ROM BAR
  PCI: Make early dump functionality generic
  PCI: Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling
  PCI: Restore resized BAR state on resume
  PCI: Clean up resource allocation in devm_of_pci_get_host_bridge_resources()

# Conflicts:
#	Documentation/admin-guide/kernel-parameters.txt
2018-08-15 14:59:01 -05:00
Bjorn Helgaas
c689209be2 Merge branch 'pci/peer-to-peer'
- Add "pci=disable_acs_redir=" parameter to disable ACS redirection for
    peer-to-peer DMA support (we don't have the peer-to-peer support yet;
    this is just one piece) (Logan Gunthorpe)

* pci/peer-to-peer:
  PCI: Add ACS Redirect disable quirk for Intel Sunrise Point
  PCI: Add device-specific ACS Redirect disable infrastructure
  PCI: Convert device-specific ACS quirks from NULL termination to ARRAY_SIZE
  PCI: Add "pci=disable_acs_redir=" parameter for peer-to-peer support
  PCI: Allow specifying devices using a base bus and path of devfns
  PCI: Make specifying PCI devices in kernel parameters reusable
  PCI: Hide ACS quirk declarations inside PCI core
2018-08-15 14:58:58 -05:00
Bjorn Helgaas
11c1a8e1f4 Merge branch 'pci/msi'
- Set IRQCHIP_ONESHOT_SAFE for PCI MSI irqchips (Heiner Kallweit)

* pci/msi:
  PCI/MSI: Set IRQCHIP_ONESHOT_SAFE for PCI-MSI irqchips
2018-08-15 14:58:56 -05:00
Bjorn Helgaas
a40f72db8a Merge branch 'pci/misc'
- Mark fall-through switch cases before enabling -Wimplicit-fallthrough
    (Gustavo A. R. Silva)

  - Move DMA-debug PCI init from arch code to PCI core (Christoph Hellwig)

  - Fix pci_request_irq() usage of IRQF_ONESHOT when no handler is supplied
    (Heiner Kallweit)

  - Unify PCI and DMA direction #defines (Shunyong Yang)

  - Add PCI_DEVICE_DATA() macro (Andy Shevchenko)

  - Check for VPD completion before checking for timeout (Bert Kenward)

  - Limit Netronome NFP5000 config space size to work around erratum (Jakub
    Kicinski)

* pci/misc:
  PCI: Limit config space size for Netronome NFP5000
  PCI/VPD: Check for VPD access completion before checking for timeout
  PCI: Add PCI_DEVICE_DATA() macro to fully describe device ID entry
  PCI: Unify PCI and normal DMA direction definitions
  PCI: Use IRQF_ONESHOT if pci_request_irq() called with no handler
  PCI: Call dma_debug_add_bus() for pci_bus_type from PCI core
  PCI: Mark fall-through switch cases before enabling -Wimplicit-fallthrough

# Conflicts:
#	drivers/pci/hotplug/pciehp_ctrl.c
2018-08-15 14:58:54 -05:00
Bjorn Helgaas
c0638a4553 Merge branch 'pci/hotplug'
- Simplify SHPC existence/permission checks (Bjorn Helgaas)

  - Remove hotplug sample skeleton driver (Lukas Wunner)

  - Convert pciehp to threaded IRQ handling (Lukas Wunner)

  - Improve pciehp tolerance of missed events and initially unstable links
    (Lukas Wunner)

  - Clear spurious pciehp events on resume (Lukas Wunner)

  - Add pciehp runtime PM support, including for Thunderbolt controllers
    (Lukas Wunner)

  - Support interrupts from pciehp bridges in D3hot (Lukas Wunner)

* pci/hotplug:
  PCI: pciehp: Deduplicate presence check on probe & resume
  PCI: pciehp: Avoid implicit fallthroughs in switch statements
  PCI: Whitelist Thunderbolt ports for runtime D3
  PCI: Whitelist native hotplug ports for runtime D3
  PCI: sysfs: Resume to D0 on function reset
  PCI: pciehp: Resume parent to D0 on config space access
  PCI: pciehp: Resume to D0 on enable/disable
  PCI: pciehp: Support interrupts sent from D3hot
  PCI: pciehp: Obey compulsory command delay after resume
  PCI: pciehp: Clear spurious events earlier on resume
  PCI: portdrv: Deduplicate PM callback iterator
  PCI: pciehp: Avoid slot access during reset
  PCI: pciehp: Always enable occupied slot on probe
  PCI: pciehp: Become resilient to missed events
  PCI: pciehp: Tolerate initially unstable link
  PCI: pciehp: Declare pciehp_enable/disable_slot() static
  PCI: pciehp: Drop enable/disable lock
  PCI: pciehp: Enable/disable exclusively from IRQ thread
  PCI: pciehp: Track enable/disable status
  PCI: pciehp: Publish to user space last on probe
  PCI: hotplug: Demidlayer registration with the core
  PCI: pciehp: Drop slot workqueue
  PCI: pciehp: Handle events synchronously
  PCI: pciehp: Stop blinking on slot enable failure
  PCI: pciehp: Convert to threaded polling
  PCI: pciehp: Convert to threaded IRQ
  PCI: pciehp: Document struct slot and struct controller
  PCI: pciehp: Declare pciehp_unconfigure_device() void
  PCI: pciehp: Drop unnecessary NULL pointer check
  PCI: pciehp: Fix unprotected list iteration in IRQ handler
  PCI: pciehp: Fix use-after-free on unplug
  PCI: hotplug: Don't leak pci_slot on registration failure
  PCI: hotplug: Delete skeleton driver
  PCI: shpchp: Separate existence of SHPC and permission to use it
2018-08-15 14:58:52 -05:00
Bjorn Helgaas
a8bcb5e596 Merge branch 'pci/enumeration'
- Work around IDT switch ACS Source Validation erratum (James
    Puthukattukaran)

  - Emit diagnostics for all cases of PCIe Link downtraining (Links
    operating slower than they're capable of) (Alexandru Gagniuc)

  - Skip VFs when configuring Max Payload Size (Myron Stowe)

  - Reduce Root Port Max Payload Size if necessary when hot-adding a device
    below it (Myron Stowe)

* pci/enumeration:
  PCI: Match Root Port's MPS to endpoint's MPSS as necessary
  PCI: Skip MPS logic for Virtual Functions (VFs)
  PCI: Check for PCIe Link downtraining
  PCI: Workaround IDT switch ACS Source Validation erratum
2018-08-15 14:58:52 -05:00
Bjorn Helgaas
1ca358a8e3 Merge branch 'pci/dpc'
- Defer DPC event handling to work queue (Keith Busch)

  - Use threaded IRQ for DPC bottom half (Keith Busch)

  - Print AER status while handling DPC events (Keith Busch)

* pci/dpc:
  PCI/DPC: Remove indirection waiting for inactive link
  PCI/DPC: Use threaded IRQ for bottom half handling
  PCI/DPC: Print AER status in DPC event handling
  PCI/DPC: Remove rp_pio_status from dpc struct
  PCI/DPC: Defer event handling to work queue
  PCI/DPC: Leave interrupts enabled while handling event
2018-08-15 14:58:51 -05:00
Bjorn Helgaas
187dacce19 Merge branch 'pci/aspm'
- Use sysfs_match_string() to simplify ASPM sysfs parsing (Andy
    Shevchenko)

  - Remove unnecessary includes of <linux/pci-aspm.h> (Bjorn Helgaas)

* pci/aspm:
  PCI: Remove unnecessary include of <linux/pci-aspm.h>
  iwlwifi: Remove unnecessary include of <linux/pci-aspm.h>
  ath9k: Remove unnecessary include of <linux/pci-aspm.h>
  igb: Remove unnecessary include of <linux/pci-aspm.h>
  PCI/ASPM: Convert to use sysfs_match_string() helper
2018-08-15 14:58:46 -05:00
Bjorn Helgaas
3c3ab37f4c Merge branch 'pci/aer'
- Decode AER errors with names similar to "lspci" (Tyler Baicar)

  - Expose AER statistics in sysfs (Rajat Jain)

  - Clear AER status bits selectively based on the type of recovery (Oza
    Pawandeep)

  - Honor "pcie_ports=native" even if HEST sets FIRMWARE_FIRST (Alexandru
    Gagniuc)

  - Don't clear AER status bits if we're using the "Firmware-First"
    strategy where firmware owns the registers (Alexandru Gagniuc)

* pci/aer:
  PCI/AER: Don't clear AER bits if error handling is Firmware-First
  PCI/AER: Remove duplicate PCI_EXP_AER_FLAGS definition
  PCI/portdrv: Remove pcie_portdrv_err_handler.slot_reset
  PCI/AER: Clear device status bits during ERR_COR handling
  PCI/AER: Clear device status bits during ERR_FATAL and ERR_NONFATAL
  PCI/AER: Remove ERR_FATAL code from ERR_NONFATAL path
  PCI/AER: Factor out ERR_NONFATAL status bit clearing
  PCI/AER: Clear only ERR_NONFATAL bits during non-fatal recovery
  PCI/AER: Clear only ERR_FATAL status bits during fatal recovery
  PCI/AER: Honor "pcie_ports=native" even if HEST sets FIRMWARE_FIRST
  PCI/AER: Add sysfs attributes for rootport cumulative stats
  PCI/AER: Add sysfs attributes to provide AER stats and breakdown
  PCI/AER: Define aer_stats structure for AER capable devices
  PCI/AER: Move internal declarations to drivers/pci/pci.h
  PCI/AER: Adopt lspci names for AER error decoding
  PCI/AER: Expose internal API for obtaining AER information

# Conflicts:
#	drivers/pci/pci.h
2018-08-15 14:58:45 -05:00
Alexandru Gagniuc
45687f96c1 PCI/AER: Don't clear AER bits if error handling is Firmware-First
If the platform requests Firmware-First error handling, firmware is
responsible for reading and clearing AER status bits.  If OSPM also clears
them, we may miss errors.  See ACPI v6.2, sec 18.3.2.5 and 18.4.

This race is mostly of theoretical significance, as it is not easy to
reasonably demonstrate it in testing.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[bhelgaas: add similar guards to pci_cleanup_aer_uncorrect_error_status()
and pci_aer_clear_fatal_status()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-15 14:35:40 -05:00
Jakub Kicinski
2538fb89b8 PCI: Limit config space size for Netronome NFP5000
Like the NFP4000 and NFP6000, the NFP5000 as an erratum where reading/
writing to PCI config space addresses above 0x600 can cause the NFP to
generate PCIe completion timeouts.

Limit the NFP5000's PF's config space size to 0x600 bytes as is already
done for the NFP4000 and NFP6000.

The NFP5000's VF is 0x6003 (PCI_DEVICE_ID_NETRONOME_NFP6000_VF), the same
device ID as the NFP6000's VF.  Thus, its config space is already limited
by the existing use of quirk_nfp6000().

Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Tony Egan <tony.egan@netronome.com>
2018-08-14 19:10:14 -05:00
Heiner Kallweit
923aa4c378 PCI/MSI: Set IRQCHIP_ONESHOT_SAFE for PCI-MSI irqchips
If flag IRQCHIP_ONESHOT_SAFE isn't set for an irqchip and we have a
threaded interrupt with no primary handler, flag IRQF_ONESHOT needs to be
set for the interrupt, causing some overhead in the threaded interrupt
handler.  For more detailed explanation also check following comment in
__setup_irq():

  The interrupt was requested with handler = NULL, so we use the default
  primary handler for it. But it does not have the oneshot flag set.  In
  combination with level interrupts this is deadly, because the default
  primary handler just wakes the thread, then the irq lines is reenabled,
  but the device still has the level irq asserted.  Rinse and repeat....

  While this works for edge type interrupts, we play it safe and reject
  unconditionally because we can't say for sure which type this interrupt
  really has.  The type flags are unreliable as the underlying chip
  implementation can override them.

Another comment in __setup_irq() gives a hint already that this
overhead can be avoided for PCI-MSI:

  Some irq chips like MSI based interrupts are per se one shot safe.  Check
  the chip flags, so we can avoid the unmask dance at the end of the
  threaded handler for those.

Following this let's mark all PCI-MSI irqchips as oneshot-safe.

See also discussion here:
https://lkml.kernel.org/r/alpine.DEB.2.21.1808032136490.1658@nanos.tec.linutronix.de

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-14 16:11:02 -05:00
Bert Kenward
6eaf278113 PCI/VPD: Check for VPD access completion before checking for timeout
Previously we checked the timeout before checking the VPD access completion
bit.  On a very heavily loaded system this can cause VPD access to timeout.
Check the completion bit before checking the timeout.

Signed-off-by: Bert Kenward <bkenward@solarflare.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-14 16:04:46 -05:00
Myron Stowe
9f0e893597 PCI: Match Root Port's MPS to endpoint's MPSS as necessary
In commit 27d868b5e6cf ("PCI: Set MPS to match upstream bridge"), we made
sure every device's MPS setting matches its upstream bridge, making it more
likely that a hot-added device will work in a system with an optimized MPS
configuration.

Recently I've started encountering systems where the endpoint device's MPSS
capability is less than its Root Port's current MPS value, thus the
endpoint is not capable of matching its upstream bridge's MPS setting (see:
bugzilla via "Link:" below).  This leaves the system vulnerable - the
upstream Root Port could respond with larger TLPs than the device can
handle, and the device will consider them to be 'Malformed'.

One could use the "pci=pcie_bus_safe" kernel parameter to work around the
issue, but that forces a user to supply a kernel parameter to get the
system to function reliably and may end up limiting MPS settings of other
unrelated, sub-topologies which could benefit from maintaining their larger
values.

Augment Keith's approach to include tuning down a Root Port's MPS setting
when its hot-added endpoint device is not capable of matching it.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=200527
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jon Mason <jdmason@kudzu.us>
Cc: Keith Busch <keith.busch@intel.com>
Cc: Sinan Kaya <okaya@kernel.org>
Cc: Dongdong Liu <liudongdong3@huawei.com>
2018-08-14 09:09:33 -05:00
Myron Stowe
3dbe97efe8 PCI: Skip MPS logic for Virtual Functions (VFs)
PCIe r4.0, sec 9.3.5.4, "Device Control Register", shows both
Max_Payload_Size (MPS) and Max_Read_request_Size (MRRS) to be 'RsvdP' for
VFs.  Just prior to the table it states:

  "PF and VF functionality is defined in Section 7.5.3.4 except where
   noted in Table 9-16.  For VF fields marked 'RsvdP', the PF setting
   applies to the VF."

All of which implies that with respect to Max_Payload_Size Supported
(MPSS), MPS, and MRRS values, we should not be paying any attention to the
VF's fields, but rather only to the PF's.  Only looking at the PF's fields
also logically makes sense as it's the sole physical interface to the PCIe
bus.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=200527
Fixes: 27d868b5e6cf ("PCI: Set MPS to match upstream bridge")
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # 4.3+
Cc: Keith Busch <keith.busch@intel.com>
Cc: Sinan Kaya <okaya@kernel.org>
Cc: Dongdong Liu <liudongdong3@huawei.com>
Cc: Jon Mason <jdmason@kudzu.us>
2018-08-14 09:07:31 -05:00
Bjorn Helgaas
7695e73f3d PCI: Add function 1 DMA alias quirk for Marvell 88SS9183
Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134
Reported-and-tested-by: Felix Blüthner <f.bluethner@mailbox.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-13 14:30:41 -05:00
Alexandru Gagniuc
2d1ce5ec21 PCI: Check for PCIe Link downtraining
When both ends of a PCIe Link are capable of a higher bandwidth than is
currently in use, the Link is said to be "downtrained".  A downtrained Link
may indicate hardware or configuration problems in the system, but it's
hard to identify such Links from userspace.

Refactor pcie_print_link_status() so it continues to always print PCIe
bandwidth information, as several NIC drivers desire.

Add a new internal __pcie_print_link_status() to emit a message only when a
device's bandwidth is constrained by the fabric and call it from the PCI
core for all devices, which identifies all downtrained Links.  It also
emits messages for a few cases that are technically not downtrained, such
as a x4 device in an open-ended x1 slot.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[bhelgaas: changelog, move __pcie_print_link_status() declaration to
drivers/pci/, rename pcie_check_upstream_link() to
pcie_report_downtraining()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-10 12:29:04 -05:00
Logan Gunthorpe
10dbc9fedc PCI: Add ACS Redirect disable quirk for Intel Sunrise Point
Intel Sunrise Point PCH hardware has an implementation of the ACS bits that
does not comply with the PCIe standard.  Add a device-specific quirk,
pci_quirk_disable_intel_spt_pch_acs_redir() to disable ACS Redirection on
this system.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: changelog, split to separate patch]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-09 17:59:07 -05:00
Logan Gunthorpe
73c47ddef2 PCI: Add device-specific ACS Redirect disable infrastructure
Intel Sunrise Point (SPT) PCH hardware has an implementation of the ACS
bits that does not comply with the PCIe standard.  To deal with this we
need device-specific quirks to disable ACS redirection.

Add a new pci_dev_specific_disable_acs_redir() quirk and a new
.disable_acs_redir() function pointer for use by non-compliant devices.  No
functional change intended.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: split to separate patch, move
pci_dev_specific_disable_acs_redir() declarations to drivers/pci/pci.h]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-09 17:48:28 -05:00
Logan Gunthorpe
3b269185c1 PCI: Convert device-specific ACS quirks from NULL termination to ARRAY_SIZE
Convert the search for device-specific ACS enable quirks from searching a
NULL-terminated array to iterating through the array, which is always
fixed-size anyway.  No functional change intended.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: changelog, split to separate patch for reviewability]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-09 17:47:44 -05:00
Logan Gunthorpe
aaca43fda7 PCI: Add "pci=disable_acs_redir=" parameter for peer-to-peer support
To support peer-to-peer traffic on a segment of the PCI hierarchy, we must
disable the ACS redirect bits for select PCI bridges.  The bridges must be
selected before the devices are discovered by the kernel and the IOMMU
groups created.  Therefore, add a kernel command line parameter to specify
devices which must have their ACS bits disabled.

The new parameter takes a list of devices separated by a semicolon.  Each
device specified will have its ACS redirect bits disabled.  This is
similar to the existing 'resource_alignment' parameter.

The ACS Request P2P Request Redirect, P2P Completion Redirect and P2P
Egress Control bits are disabled, which is sufficient to always allow
passing P2P traffic uninterrupted.  The bits are set after the kernel
(optionally) enables the ACS bits itself.  It is also done regardless of
whether the kernel or platform firmware sets the bits.

If the user tries to disable the ACS redirect for a device without the ACS
capability, print a warning to dmesg.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: reorder to add the generic code first and move the
device-specific quirk to subsequent patches]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Bates <sbates@raithlin.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-08-09 17:37:19 -05:00
Logan Gunthorpe
45db33709c PCI: Allow specifying devices using a base bus and path of devfns
When specifying PCI devices on the kernel command line using a
bus/device/function address, bus numbers can change when adding or
replacing a device, changing motherboard firmware, or applying kernel
parameters like "pci=assign-buses".  When bus numbers change, it's likely
the command line tweak will be applied to the wrong device.

Therefore, it is useful to be able to specify devices with a base bus
number and the path of devfns needed to get to it, similar to the "device
scope" structure in the Intel VT-d spec, Section 8.3.1.

Thus, we add an option to specify devices in the following format:

  [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*

The path can be any segment within the PCI hierarchy of any length and
determined through the use of 'lspci -t'.  When specified this way, it is
less likely that a renumbered bus will result in a valid device
specification and the tweak won't be applied to the wrong device.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: use "device" instead of "slot" in documentation since that's the
usual language in the PCI specs]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Bates <sbates@raithlin.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-08-09 16:24:39 -05:00
Logan Gunthorpe
07d8d7e57c PCI: Make specifying PCI devices in kernel parameters reusable
Separate out the code to match a PCI device with a string (typically
originating from a kernel parameter) from the
pci_specified_resource_alignment() function into its own helper function.

While we are at it, this change fixes the kernel style of the function
(fixing a number of long lines and extra parentheses).

Additionally, make the analogous change to the kernel parameter
documentation: Separate the description of how to specify a PCI device
into its own section at the head of the "pci=" parameter.

This patch should have no functional alterations.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: use "device" instead of "slot" in documentation since that's the
usual language in the PCI specs]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Bates <sbates@raithlin.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-08-09 16:23:06 -05:00
Bjorn Helgaas
bd2e9567db PCI: Hide ACS quirk declarations inside PCI core
Move declarations for these functions:

  pci_dev_specific_acs_enabled()
  pci_dev_specific_enable_acs()

from include/linux/pci.h to drivers/pci/pci.h because nothing outside the
PCI core needs to use them.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-09 16:19:52 -05:00
Alex Williamson
51ba09452d PCI: Delay after FLR of Intel DC P3700 NVMe
Add a device-specific reset for Intel DC P3700 NVMe device which exhibits a
timeout failure in drivers waiting for the ready status to update after
NVMe enable if the driver interacts with the device too soon after FLR.  As
this has been observed in device assignment scenarios, resolve this with a
device-specific reset quirk to add an additional, heuristically determined,
delay after the FLR completes.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1592654
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-09 15:20:52 -05:00
Alex Williamson
ffb0863426 PCI: Disable Samsung SM961/PM961 NVMe before FLR
The Samsung SM961/PM961 (960 EVO) sometimes fails to return from FLR with
the PCI config space reading back as -1.  A reproducible instance of this
behavior is resolved by clearing the enable bit in the NVMe configuration
register and waiting for the ready status to clear (disabling the NVMe
controller) prior to FLR.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1542494
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-09 15:18:33 -05:00
Alex Williamson
2d2917f774 PCI: Export pcie_has_flr()
pcie_flr() suggests pcie_has_flr() to ensure that PCIe FLR support is
present prior to calling.  pcie_flr() is exported while pcie_has_flr()
is not.  Resolve this.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-09 15:18:27 -05:00
Thomas Petazzoni
f23d0d449c PCI: mvebu: Drop bogus comment above mvebu_pcie_map_registers()
This comment has been there since the driver was introduced, but seems
to be a leftover from previous iterations of the driver. Indeed, we do
not lookup in a list to find the register ranges that matches the
given port/lane, as the "reg" property is in each sub-node
representing a PCI port. There is no lookup involved at all.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-08 15:58:18 +01:00
Thomas Petazzoni
42342073e3 PCI: mvebu: Convert to use pci_host_bridge directly
Rather than using the ARM-specific pci_common_init_dev() API, use the
pci_host_bridge logic directly.

Unfortunately, we can't use devm_of_pci_get_host_bridge_resources(),
because the DT binding for describing PCIe apertures for this PCI
controller is a bit special, and we cannot retrieve them from the
'ranges' property. Therefore, we still have some special code to
handle this.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-08 15:57:50 +01:00
Thomas Petazzoni
5a553d6ba1 PCI: mvebu: Use resource_size() to remap I/O space
Instead of hardcoding the remapping of IO_SPACE_LIMIT - SZ_64K, use
resource_size().

However, we cannot use just IO_SPACE_LIMIT, because pci_ioremap_io() has
a bug and doesn't allow remapping the last 64 KB before IO_SPACE_LIMIT,
so we ensure that we do not exceed this limit. When the pci_ioremap_io()
issue is fixed, this work around can be dropped.

Note that this workaround already existed, since we were mapping only
up to IO_SPACE_LIMIT - SZ_64K.

Suggested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
[lorenzo.pieralisi@arm.com: tweaked the commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-08 15:51:06 +01:00
Thomas Petazzoni
ee1604381a PCI: mvebu: Only remap I/O space if configured
If there is no PCI I/O aperture configured in the Device Tree, it does
not make sense to create the virtual mapping for the PCI I/O space,
since we will anyway not create the MBus window that will allow to
access it. Therefore, do the pci_ioremap_io() only if necessary.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-08 15:50:30 +01:00
Thomas Petazzoni
dfd0309fd7 PCI: mvebu: Fix I/O space end address calculation
pcie->realio.end should be the address of last byte of the area,
therefore using resource_size() of another resource is not correct, we
must substract 1 to get the address of the last byte.

Fixes: 11be65472a427 ("PCI: mvebu: Adapt to the new device tree layout")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-08 15:50:04 +01:00
Thomas Petazzoni
6554f95019 PCI: mvebu: Remove redundant platform_set_drvdata() call
This is already done earlier in mvebu_pcie_probe().

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-08 15:49:52 +01:00
Bjorn Helgaas
ce29af2a50 PCI: Remove unnecessary include of <linux/pci-aspm.h>
Several PCI core files include pci-aspm.h even though they don't need
anything provided by that file.  Remove the unnecessary includes of it.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sinan Kaya <okaya@kernel.org>
2018-08-06 14:32:22 -05:00
Andy Shevchenko
36131ce9a0 PCI/ASPM: Convert to use sysfs_match_string() helper
The sysfs_match_string() helper returns index of the matching string in an
array.  Use it in pcie_aspm_set_policy() to simplify the code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
[bhelgaas: squash sysfs_match_string() fix into original patch for issue
Reported-by: Heiner Kallweit <hkallweit1@gmail.com>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-08-06 14:30:34 -05:00
Christoph Hellwig
34dbc9c658 PCI/xilinx: Depend on OF instead of the ARCH
There isn't a hard dependency of the Xilinx AXI-PCIe host bridge on any
architecture.  For example: at SiFive we map RISC-V cores to Xilinx FPGAs
and connect the Xilinx IP via a TileLink adapter, so the RISC-V Linux
port will need to be able to enable PCIE_XILINX in order to have PCIe
support.

This patch decouples the PCIE_XILINX support from ARCH.  Instead it just
depends on OF, which is the only true dependency.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
[hch: switch to OF instead of OF_PCI now that the latter is gone]
Signed-off-by: Christoph Hellwig <hch@lst.de>
[lorenzo.pieralisi@arm.com: trimmed the commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-08-06 11:39:08 +01:00
Bjorn Helgaas
944d58595b PCI/AER: Remove duplicate PCI_EXP_AER_FLAGS definition
PCI_EXP_AER_FLAGS was defined twice (with identical definitions), once
under #ifdef CONFIG_ACPI_APEI, and again at the top level.  This looks like
my merge error from these commits:

  fd3362cb73de ("PCI/AER: Squash aerdrv_core.c into aerdrv.c")
  41cbc9eb1a82 ("PCI/AER: Squash ecrc.c into aerdrv.c")

Remove the duplicate PCI_EXP_AER_FLAGS definition.

Fixes: 41cbc9eb1a82 ("PCI/AER: Squash ecrc.c into aerdrv.c")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
2018-07-31 16:26:09 -05:00
Lukas Wunner
4e6a13356f PCI: pciehp: Deduplicate presence check on probe & resume
On driver probe and on resume from system sleep, pciehp checks the
Presence Detect State bit in the Slot Status register to bring up an
occupied slot or bring down an unoccupied slot.  Both code paths are
identical, so deduplicate them per Mika's request.

On probe, an additional check is performed to disable power of an
unoccupied slot.  This can e.g. happen if power was enabled by BIOS.
It cannot happen once pciehp has taken control, hence is not necessary
on resume:  The Slot Control register is set to the same value that it
had on suspend by pci_restore_state(), so if the slot was occupied,
power is enabled and if it wasn't, power is disabled.  Should occupancy
have changed during the system sleep transition, power is adjusted by
bringing up or down the slot per the paragraph above.

To allow for deduplication of the presence check, move the power check
to pcie_init().  This seems safer anyway, because right now it is
performed while interrupts are already enabled, and although I can't
think of a scenario where pciehp_power_off_slot() and the IRQ thread
collide, it does feel brittle.

However this means that pcie_init() may now write to the Slot Control
register before the IRQ is requested.  If both the CCIE and HPIE bits
happen to be set, pcie_wait_cmd() will wait for an interrupt (instead
of polling the Command Completed bit) and eventually emit a timeout
message.  Additionally, if a level-triggered INTx interrupt is used,
the user may see a spurious interrupt splat.  Avoid by disabling
interrupts before disabling power.  (Normally the HPIE and CCIE bits
should be clear on probe, but conceivably they may already have been
set e.g. by BIOS.)

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-07-31 13:27:24 -05:00
Lukas Wunner
8bb46b079d PCI: pciehp: Avoid implicit fallthroughs in switch statements
Per Mika's request, add an explicit break to the last case of switch
statements everywhere in pciehp to be more defensive towards future
amendments.

Per Gustavo's request, mark all non-empty implicit fallthroughs with a
comment to silence warnings triggered by -Wimplicit-fallthrough=2.

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
2018-07-31 13:26:33 -05:00