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430ad3f0dd
APECS is the DECchip 21071x chipset for the EV4 and EV45 generation, while LCA is the integrated I/O support on the corresponding low-cost alpha machines of that generation. All of these CPUs lack the BWX extension for byte and word access, so drop the chipset support and all associated machines. Acked-by: Paul E. McKenney <paulmck@kernel.org> Acked-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
160 lines
3.8 KiB
C
160 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/alpha/kernel/irq_i8259.c
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*
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* This is the 'legacy' 8259A Programmable Interrupt Controller,
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* present in the majority of PC/AT boxes.
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*
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* Started hacking from linux-2.3.30pre6/arch/i386/kernel/i8259.c.
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*/
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#include <linux/init.h>
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#include <linux/cache.h>
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#include <linux/sched.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include "proto.h"
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#include "irq_impl.h"
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/* Note mask bit is true for DISABLED irqs. */
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static unsigned int cached_irq_mask = 0xffff;
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static DEFINE_SPINLOCK(i8259_irq_lock);
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static inline void
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i8259_update_irq_hw(unsigned int irq, unsigned long mask)
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{
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int port = 0x21;
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if (irq & 8) mask >>= 8;
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if (irq & 8) port = 0xA1;
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outb(mask, port);
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}
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inline void
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i8259a_enable_irq(struct irq_data *d)
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{
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spin_lock(&i8259_irq_lock);
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i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
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spin_unlock(&i8259_irq_lock);
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}
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static inline void
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__i8259a_disable_irq(unsigned int irq)
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{
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i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
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}
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void
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i8259a_disable_irq(struct irq_data *d)
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{
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spin_lock(&i8259_irq_lock);
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__i8259a_disable_irq(d->irq);
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spin_unlock(&i8259_irq_lock);
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}
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void
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i8259a_mask_and_ack_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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spin_lock(&i8259_irq_lock);
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__i8259a_disable_irq(irq);
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/* Ack the interrupt making it the lowest priority. */
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if (irq >= 8) {
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outb(0xE0 | (irq - 8), 0xa0); /* ack the slave */
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irq = 2;
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}
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outb(0xE0 | irq, 0x20); /* ack the master */
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spin_unlock(&i8259_irq_lock);
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}
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struct irq_chip i8259a_irq_type = {
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.name = "XT-PIC",
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.irq_unmask = i8259a_enable_irq,
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.irq_mask = i8259a_disable_irq,
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.irq_mask_ack = i8259a_mask_and_ack_irq,
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};
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void __init
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init_i8259a_irqs(void)
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{
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long i;
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outb(0xff, 0x21); /* mask all of 8259A-1 */
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outb(0xff, 0xA1); /* mask all of 8259A-2 */
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for (i = 0; i < 16; i++) {
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irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
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}
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if (request_irq(2, no_action, 0, "cascade", NULL))
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pr_err("Failed to request irq 2 (cascade)\n");
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}
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#if defined(CONFIG_ALPHA_GENERIC)
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# define IACK_SC alpha_mv.iack_sc
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#elif defined(CONFIG_ALPHA_CIA)
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# define IACK_SC CIA_IACK_SC
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#elif defined(CONFIG_ALPHA_PYXIS)
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# define IACK_SC PYXIS_IACK_SC
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#elif defined(CONFIG_ALPHA_TITAN)
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# define IACK_SC TITAN_IACK_SC
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#elif defined(CONFIG_ALPHA_TSUNAMI)
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# define IACK_SC TSUNAMI_IACK_SC
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#elif defined(CONFIG_ALPHA_IRONGATE)
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# define IACK_SC IRONGATE_IACK_SC
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#endif
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/* Note that CONFIG_ALPHA_POLARIS is intentionally left out here, since
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sys_rx164 wants to use isa_no_iack_sc_device_interrupt for some reason. */
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#if defined(IACK_SC)
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void
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isa_device_interrupt(unsigned long vector)
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{
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/*
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* Generate a PCI interrupt acknowledge cycle. The PIC will
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* respond with the interrupt vector of the highest priority
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* interrupt that is pending. The PALcode sets up the
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* interrupts vectors such that irq level L generates vector L.
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*/
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int j = *(vuip) IACK_SC;
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j &= 0xff;
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handle_irq(j);
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}
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || !defined(IACK_SC)
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void
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isa_no_iack_sc_device_interrupt(unsigned long vector)
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{
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unsigned long pic;
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/*
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* It seems to me that the probability of two or more *device*
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* interrupts occurring at almost exactly the same time is
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* pretty low. So why pay the price of checking for
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* additional interrupts here if the common case can be
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* handled so much easier?
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*/
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/*
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* The first read of gives you *all* interrupting lines.
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* Therefore, read the mask register and and out those lines
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* not enabled. Note that some documentation has 21 and a1
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* write only. This is not true.
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*/
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pic = inb(0x20) | (inb(0xA0) << 8); /* read isr */
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pic &= 0xFFFB; /* mask out cascade & hibits */
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while (pic) {
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int j = ffz(~pic);
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pic &= pic - 1;
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handle_irq(j);
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}
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}
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#endif
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