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40a895fd9a
Group all cxl related kernel headers into include/cxl/ directory. Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20240905223711.1990186-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
176 lines
3.7 KiB
C
176 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2023 Intel Corporation. */
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#ifndef _LINUX_CXL_EVENT_H
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#define _LINUX_CXL_EVENT_H
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#include <linux/types.h>
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#include <linux/uuid.h>
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#include <linux/workqueue_types.h>
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/*
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* Common Event Record Format
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* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
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*/
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struct cxl_event_record_hdr {
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u8 length;
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u8 flags[3];
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__le16 handle;
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__le16 related_handle;
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__le64 timestamp;
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u8 maint_op_class;
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u8 reserved[15];
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} __packed;
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struct cxl_event_media_hdr {
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struct cxl_event_record_hdr hdr;
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__le64 phys_addr;
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u8 descriptor;
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u8 type;
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u8 transaction_type;
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/*
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* The meaning of Validity Flags from bit 2 is
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* different across DRAM and General Media records
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*/
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u8 validity_flags[2];
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u8 channel;
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u8 rank;
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} __packed;
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#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
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struct cxl_event_generic {
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struct cxl_event_record_hdr hdr;
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u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
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} __packed;
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/*
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* General Media Event Record
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* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
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*/
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#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
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struct cxl_event_gen_media {
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struct cxl_event_media_hdr media_hdr;
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u8 device[3];
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u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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u8 reserved[46];
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} __packed;
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/*
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* DRAM Event Record - DER
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* CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
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*/
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#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
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struct cxl_event_dram {
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struct cxl_event_media_hdr media_hdr;
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u8 nibble_mask[3];
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u8 bank_group;
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u8 bank;
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u8 row[3];
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u8 column[2];
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u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
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u8 reserved[0x17];
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} __packed;
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/*
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* Get Health Info Record
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* CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
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*/
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struct cxl_get_health_info {
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u8 health_status;
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u8 media_status;
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u8 add_status;
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u8 life_used;
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u8 device_temp[2];
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u8 dirty_shutdown_cnt[4];
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u8 cor_vol_err_cnt[4];
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u8 cor_per_err_cnt[4];
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} __packed;
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/*
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* Memory Module Event Record
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* CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
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*/
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struct cxl_event_mem_module {
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struct cxl_event_record_hdr hdr;
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u8 event_type;
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struct cxl_get_health_info info;
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u8 reserved[0x3d];
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} __packed;
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union cxl_event {
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struct cxl_event_generic generic;
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struct cxl_event_gen_media gen_media;
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struct cxl_event_dram dram;
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struct cxl_event_mem_module mem_module;
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/* dram & gen_media event header */
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struct cxl_event_media_hdr media_hdr;
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} __packed;
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/*
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* Common Event Record Format; in event logs
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* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
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*/
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struct cxl_event_record_raw {
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uuid_t id;
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union cxl_event event;
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} __packed;
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enum cxl_event_type {
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CXL_CPER_EVENT_GENERIC,
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CXL_CPER_EVENT_GEN_MEDIA,
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CXL_CPER_EVENT_DRAM,
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CXL_CPER_EVENT_MEM_MODULE,
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};
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#define CPER_CXL_DEVICE_ID_VALID BIT(0)
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#define CPER_CXL_DEVICE_SN_VALID BIT(1)
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#define CPER_CXL_COMP_EVENT_LOG_VALID BIT(2)
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struct cxl_cper_event_rec {
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struct {
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u32 length;
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u64 validation_bits;
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struct cper_cxl_event_devid {
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u16 vendor_id;
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u16 device_id;
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u8 func_num;
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u8 device_num;
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u8 bus_num;
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u16 segment_num;
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u16 slot_num; /* bits 2:0 reserved */
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u8 reserved;
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} __packed device_id;
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struct cper_cxl_event_sn {
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u32 lower_dw;
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u32 upper_dw;
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} __packed dev_serial_num;
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} __packed hdr;
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union cxl_event event;
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} __packed;
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struct cxl_cper_work_data {
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enum cxl_event_type event_type;
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struct cxl_cper_event_rec rec;
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};
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#ifdef CONFIG_ACPI_APEI_GHES
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int cxl_cper_register_work(struct work_struct *work);
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int cxl_cper_unregister_work(struct work_struct *work);
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int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd);
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#else
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static inline int cxl_cper_register_work(struct work_struct *work)
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{
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return 0;
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}
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static inline int cxl_cper_unregister_work(struct work_struct *work)
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{
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return 0;
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}
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static inline int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd)
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{
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return 0;
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}
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#endif
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#endif /* _LINUX_CXL_EVENT_H */
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