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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ee3daf7c05
In the past two save areas existed because interrupt handlers and system call / program check handlers where entered with interrupts enabled. To prevent a handler from overwriting the save areas from the previous handler, interrupts used the async save area, while system call and program check handler used the sync save area. Since the removal of critical section cleanup from entry.S, handlers are entered with interrupts disabled. When the interrupts are re-enabled, the save area is no longer need. Therefore merge both save areas into one. Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
321 lines
8.9 KiB
ArmAsm
321 lines
8.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright IBM Corp. 1999, 2010
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*
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* Author(s): Hartmut Penner <hp@de.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Rob van der Heij <rvdhei@iae.nl>
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*
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* There are 5 different IPL methods
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* 1) load the image directly into ram at address 0 and do an PSW restart
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* 2) linload will load the image from address 0x10000 to memory 0x10000
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* and start the code thru LPSW 0x0008000080010000 (VM only, deprecated)
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* 3) generate the tape ipl header, store the generated image on a tape
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* and ipl from it
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* In case of SL tape you need to IPL 5 times to get past VOL1 etc
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* 4) generate the vm reader ipl header, move the generated image to the
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* VM reader (use option NOH!) and do a ipl from reader (VM only)
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* 5) direct call of start by the SALIPL loader
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* We use the cpuid to distinguish between VM and native ipl
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* params for kernel are pushed to 0x10400 (see setup.h)
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*
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/sclp.h>
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#include "boot.h"
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#define EP_OFFSET 0x10008
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#define EP_STRING "S390EP"
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#define IPL_BS 0x730
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__HEAD
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ipl_start:
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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lhi %r1,2 # mode 2 = esame (dump)
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sigp %r1,%r0,0x12 # switch to esame mode
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sam64 # switch to 64 bit addressing mode
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lgh %r1,__LC_SUBCHANNEL_ID # test if subchannel number
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brctg %r1,.Lnoload # is valid
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llgf %r1,__LC_SUBCHANNEL_ID # load ipl subchannel number
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lghi %r2,IPL_BS # load start address
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bras %r14,.Lloader # load rest of ipl image
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larl %r12,parmarea # pointer to parameter area
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stg %r1,IPL_DEVICE-PARMAREA(%r12) # save ipl device number
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#
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# load parameter file from ipl device
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#
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.Lagain1:
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larl %r2,_end # ramdisk loc. is temp
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bras %r14,.Lloader # load parameter file
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ltgr %r2,%r2 # got anything ?
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jz .Lnopf
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lg %r3,MAX_COMMAND_LINE_SIZE-PARMAREA(%r12)
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aghi %r3,-1
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clgr %r2,%r3
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jl .Lnotrunc
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lgr %r2,%r3
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.Lnotrunc:
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larl %r4,_end
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larl %r13,.L_hdr
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clc 0(3,%r4),0(%r13) # if it is HDRx
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jz .Lagain1 # skip dataset header
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larl %r13,.L_eof
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clc 0(3,%r4),0(%r13) # if it is EOFx
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jz .Lagain1 # skip data set trailer
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lgr %r5,%r2
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la %r6,COMMAND_LINE-PARMAREA(%r12)
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lgr %r7,%r2
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aghi %r7,1
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mvcl %r6,%r4
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.Lnopf:
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#
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# load ramdisk from ipl device
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#
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.Lagain2:
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larl %r2,_end # addr of ramdisk
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stg %r2,INITRD_START-PARMAREA(%r12)
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bras %r14,.Lloader # load ramdisk
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stg %r2,INITRD_SIZE-PARMAREA(%r12) # store size of rd
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ltgr %r2,%r2
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jnz .Lrdcont
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stg %r2,INITRD_START-PARMAREA(%r12) # no ramdisk found
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.Lrdcont:
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larl %r2,_end
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larl %r13,.L_hdr # skip HDRx and EOFx
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clc 0(3,%r2),0(%r13)
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jz .Lagain2
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larl %r13,.L_eof
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clc 0(3,%r2),0(%r13)
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jz .Lagain2
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#
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# reset files in VM reader
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#
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larl %r13,.Lcpuid
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stidp 0(%r13) # store cpuid
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tm 0(%r13),0xff # running VM ?
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jno .Lnoreset
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larl %r2,.Lreset
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lghi %r3,26
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diag %r2,%r3,8
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larl %r5,.Lirb
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stsch 0(%r5) # check if irq is pending
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tm 30(%r5),0x0f # by verifying if any of the
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jnz .Lwaitforirq # activity or status control
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tm 31(%r5),0xff # bits is set in the schib
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jz .Lnoreset
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.Lwaitforirq:
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bras %r14,.Lirqwait # wait for IO interrupt
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c %r1,__LC_SUBCHANNEL_ID # compare subchannel number
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jne .Lwaitforirq
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larl %r5,.Lirb
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tsch 0(%r5)
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.Lnoreset:
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j .Lnoload
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#
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# everything loaded, go for it
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#
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.Lnoload:
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jg startup
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#
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# subroutine to wait for end I/O
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#
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.Lirqwait:
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larl %r13,.Lnewpswmask # set up IO interrupt psw
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mvc __LC_IO_NEW_PSW(8),0(%r13)
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stg %r14,__LC_IO_NEW_PSW+8
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larl %r13,.Lwaitpsw
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lpswe 0(%r13)
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.Lioint:
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#
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# subroutine for loading cards from the reader
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#
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.Lloader:
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lgr %r4,%r14
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larl %r3,.Lorb # r2 = address of orb into r2
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larl %r5,.Lirb # r4 = address of irb
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larl %r6,.Lccws
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lghi %r7,20
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.Linit:
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st %r2,4(%r6) # initialize CCW data addresses
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la %r2,0x50(%r2)
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la %r6,8(%r6)
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brctg %r7,.Linit
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larl %r13,.Lcr6
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lctlg %c6,%c6,0(%r13)
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xgr %r2,%r2
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.Lldlp:
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ssch 0(%r3) # load chunk of 1600 bytes
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jnz .Llderr
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.Lwait4irq:
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bras %r14,.Lirqwait
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c %r1,__LC_SUBCHANNEL_ID # compare subchannel number
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jne .Lwait4irq
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tsch 0(%r5)
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xgr %r0,%r0
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ic %r0,8(%r5) # get device status
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cghi %r0,8 # channel end ?
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je .Lcont
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cghi %r0,12 # channel end + device end ?
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je .Lcont
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llgf %r0,4(%r5)
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sgf %r0,8(%r3) # r0/8 = number of ccws executed
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mghi %r0,10 # *10 = number of bytes in ccws
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llgh %r3,10(%r5) # get residual count
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sgr %r0,%r3 # #ccws*80-residual=#bytes read
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agr %r2,%r0
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br %r4 # r2 contains the total size
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.Lcont:
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aghi %r2,0x640 # add 0x640 to total size
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larl %r6,.Lccws
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lghi %r7,20
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.Lincr:
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l %r0,4(%r6) # update CCW data addresses
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aghi %r0,0x640
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st %r0,4(%r6)
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aghi %r6,8
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brctg %r7,.Lincr
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j .Lldlp
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.Llderr:
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larl %r13,.Lcrash
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lpsw 0(%r13)
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.balign 8
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.Lwaitpsw:
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.quad 0x0202000180000000,.Lioint
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.Lnewpswmask:
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.quad 0x0000000180000000
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.balign 8
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.Lorb: .long 0x00000000,0x0080ff00,.Lccws
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.Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.balign 8
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.Lcr6: .quad 0x00000000ff000000
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.balign 8
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.Lcrash:.long 0x000a0000,0x00000000
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.balign 8
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.Lccws: .rept 19
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.long 0x02600050,0x00000000
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.endr
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.long 0x02200050,0x00000000
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.Lreset:.byte 0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40
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.byte 0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6
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.byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold"
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.L_eof: .long 0xc5d6c600 /* C'EOF' */
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.L_hdr: .long 0xc8c4d900 /* C'HDR' */
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.balign 8
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.Lcpuid:.fill 8,1,0
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#
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# normal startup-code, running in absolute addressing mode
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# this is called either by the ipl loader or directly by PSW restart
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# or linload or SALIPL
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#
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.org STARTUP_NORMAL_OFFSET - IPL_START
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SYM_CODE_START(startup)
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j startup_normal
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.org EP_OFFSET - IPL_START
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#
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# This is a list of s390 kernel entry points. At address 0x1000f the number of
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# valid entry points is stored.
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#
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# IMPORTANT: Do not change this table, it is s390 kernel ABI!
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#
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.ascii EP_STRING
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.byte 0x00,0x01
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#
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# kdump startup-code, running in 64 bit absolute addressing mode
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#
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.org STARTUP_KDUMP_OFFSET - IPL_START
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j startup_kdump
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SYM_CODE_END(startup)
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SYM_CODE_START_LOCAL(startup_normal)
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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lhi %r1,2 # mode 2 = esame (dump)
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sigp %r1,%r0,0x12 # switch to esame mode
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bras %r13,0f
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.fill 16,4,0x0
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0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs
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sam64 # switch to 64 bit addressing mode
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larl %r13,.Lext_new_psw
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mvc __LC_EXT_NEW_PSW(16),0(%r13)
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larl %r13,.Lpgm_new_psw
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mvc __LC_PGM_NEW_PSW(16),0(%r13)
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larl %r13,.Lio_new_psw
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mvc __LC_IO_NEW_PSW(16),0(%r13)
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xc 0x200(256),0x200 # partially clear lowcore
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xc 0x300(256),0x300
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xc 0xe00(256),0xe00
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xc 0xf00(256),0xf00
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larl %r13,.Lctl
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lctlg %c0,%c15,0(%r13) # load control registers
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stcke __LC_BOOT_CLOCK
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mvc __LC_LAST_UPDATE_CLOCK(8),__LC_BOOT_CLOCK+1
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larl %r13,6f
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spt 0(%r13)
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mvc __LC_LAST_UPDATE_TIMER(8),0(%r13)
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larl %r15,_stack_end-STACK_FRAME_OVERHEAD
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brasl %r14,sclp_early_setup_buffer
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brasl %r14,verify_facilities
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brasl %r14,startup_kernel
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SYM_CODE_END(startup_normal)
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.balign 8
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6: .long 0x7fffffff,0xffffffff
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.Lext_new_psw:
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.quad 0x0002000180000000,0x1b0 # disabled wait
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.Lpgm_new_psw:
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.quad 0x0000000180000000,startup_pgm_check_handler
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.Lio_new_psw:
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.quad 0x0002000180000000,0x1f0 # disabled wait
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.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
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.quad 0 # cr1: primary space segment table
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.quad 0 # cr2: dispatchable unit control table
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.quad 0 # cr3: instruction authorization
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.quad 0xffff # cr4: instruction authorization
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.quad 0 # cr5: primary-aste origin
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.quad 0 # cr6: I/O interrupts
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.quad 0 # cr7: secondary space segment table
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.quad 0x0000000000008000 # cr8: access registers translation
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.quad 0 # cr9: tracing off
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.quad 0 # cr10: tracing off
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.quad 0 # cr11: tracing off
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.quad 0 # cr12: tracing off
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.quad 0 # cr13: home space segment table
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.quad 0xc0000000 # cr14: machine check handling off
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.quad 0 # cr15: linkage stack operations
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#include "head_kdump.S"
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#
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# This program check is active immediately after kernel start
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# and until early_pgm_check_handler is set in kernel/early.c
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# It simply saves general/control registers and psw in
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# the save area and does disabled wait with a faulty address.
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#
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SYM_CODE_START_LOCAL(startup_pgm_check_handler)
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stmg %r8,%r15,__LC_SAVE_AREA
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la %r8,4095
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stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8)
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stmg %r0,%r7,__LC_GPREGS_SAVE_AREA-4095(%r8)
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mvc __LC_GPREGS_SAVE_AREA-4095+64(64,%r8),__LC_SAVE_AREA
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mvc __LC_PSW_SAVE_AREA-4095(16,%r8),__LC_PGM_OLD_PSW
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mvc __LC_RETURN_PSW(16),__LC_PGM_OLD_PSW
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ni __LC_RETURN_PSW,0xfc # remove IO and EX bits
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ni __LC_RETURN_PSW+1,0xfb # remove MCHK bit
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oi __LC_RETURN_PSW+1,0x2 # set wait state bit
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larl %r9,.Lold_psw_disabled_wait
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stg %r9,__LC_PGM_NEW_PSW+8
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larl %r15,_dump_info_stack_end-STACK_FRAME_OVERHEAD
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brasl %r14,print_pgm_check_info
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.Lold_psw_disabled_wait:
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la %r8,4095
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lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r8)
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lpswe __LC_RETURN_PSW # disabled wait
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SYM_CODE_END(startup_pgm_check_handler)
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