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03890f477c
* Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M * Don't init CNTVOFF/counter if PSCI is available -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAl0MksAACgkQ189kaWo3 T75qLhAAq4ezsma/ajA++m+K1zF16t4TMKt8iSLGQXANZ0rDd7zkaXZ7H0ztfrh1 WqTVUklYAR55qHWvxH+wyhT312cBg1Tx2+Jvx9IgA5nRVVylOzKAHhEj1TIfAsIZ tE6xR/oNEXGH4f97KFl6IypVPfBoG6tRK1pj59Ns0oXf4HSwRIk8tfaUQfIbfihY Z7TQ0AljthbNLpWxHyDj6VWWBSAGtRcjgV5SezgN141C1BTeRX0rovJ0gIGWFZCt NxL+kaBSAQ2h6GVy/4KPP6h/gS5IuojdJ2npuRxG0IQGieAPsm0MbxD2YmXWzCLX rz3PmCgoKd9fvRYZw4YhG7FIc3wFACpcXfbImoArMelt9Th/9xPwUAoidTCg/meS ON/lVJckA5KquE89yjSJIJHrqLcXT6AKkMWPK2KqT0KP7l+MSX6hJEg6PAkEPtaQ DdrnmDcl3dMKwbEp0f7OL2dKXQvcusRZCY/eILr11RWsd/oThZ4y1magxypHUhxb iVVMRkNgaKFlMpRTCTMSAvchUOm3fiIKK75MBr0CPfFb1x7S0le2COa/5yNsnuJd rj8gTwhXlAU/BSVHzEjUnoH0JKCs1p9VYu8KiAfpgrBQOxaEhpO0tiO/EuUSTKvv xwqZGgJF93cPNKKLDzKrLp2pClL77jwxUk2sfPdr/x92Gfe1ycI= =dMJy -----END PGP SIGNATURE----- Merge tag 'renesas-arm-soc-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/soc Renesas ARM Based SoC Updates for v5.3 * Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M * Don't init CNTVOFF/counter if PSCI is available * tag 'renesas-arm-soc-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M ARM: mach-shmobile: Don't init CNTVOFF/counter if PSCI is available Signed-off-by: Olof Johansson <olof@lixom.net>