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047275f7de
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4_4B 0xec, for erases SPINOR_OP_BE_4K_4B 0x21, and for writes SPINOR_OP_PP_1_1_4_4B 0x34. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211207140254.87681-14-tudor.ambarus@microchip.com
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static void gd25q256_default_init(struct spi_nor *nor)
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{
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/*
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* Some manufacturer like GigaDevice may use different
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* bit to set QE on different memories, so the MFR can't
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* indicate the quad_enable method for this case, we need
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* to set it in the default_init fixup hook.
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*/
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static struct spi_nor_fixups gd25q256_fixups = {
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.default_init = gd25q256_default_init,
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};
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static const struct flash_info gigadevice_parts[] = {
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{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512)
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PARSE_SFDP
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &gd25q256_fixups },
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};
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const struct spi_nor_manufacturer spi_nor_gigadevice = {
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.name = "gigadevice",
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.parts = gigadevice_parts,
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.nparts = ARRAY_SIZE(gigadevice_parts),
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};
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