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154afa5c31
Extend the MAX10 BMC Secure Update driver to provide a sysfs file to expose the flash update count. Reviewed-by: Tom Rix <trix@redhat.com> Tested-by: Tianfei Zhang <tianfei.zhang@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20220606160038.846236-4-russell.h.weight@intel.com Signed-off-by: Xu Yilun <yilun.xu@intel.com>
178 lines
4.7 KiB
C
178 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel MAX10 Board Management Controller Secure Update Driver
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*
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* Copyright (C) 2019-2022 Intel Corporation. All rights reserved.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/mfd/intel-m10-bmc.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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struct m10bmc_sec {
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struct device *dev;
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struct intel_m10bmc *m10bmc;
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};
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/* Root Entry Hash (REH) support */
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#define REH_SHA256_SIZE 32
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#define REH_SHA384_SIZE 48
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#define REH_MAGIC GENMASK(15, 0)
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#define REH_SHA_NUM_BYTES GENMASK(31, 16)
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static ssize_t
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show_root_entry_hash(struct device *dev, u32 exp_magic,
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u32 prog_addr, u32 reh_addr, char *buf)
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{
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struct m10bmc_sec *sec = dev_get_drvdata(dev);
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int sha_num_bytes, i, ret, cnt = 0;
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u8 hash[REH_SHA384_SIZE];
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unsigned int stride;
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u32 magic;
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stride = regmap_get_reg_stride(sec->m10bmc->regmap);
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ret = m10bmc_raw_read(sec->m10bmc, prog_addr, &magic);
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if (ret)
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return ret;
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if (FIELD_GET(REH_MAGIC, magic) != exp_magic)
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return sysfs_emit(buf, "hash not programmed\n");
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sha_num_bytes = FIELD_GET(REH_SHA_NUM_BYTES, magic) / 8;
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if ((sha_num_bytes % stride) ||
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(sha_num_bytes != REH_SHA256_SIZE &&
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sha_num_bytes != REH_SHA384_SIZE)) {
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dev_err(sec->dev, "%s bad sha num bytes %d\n", __func__,
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sha_num_bytes);
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return -EINVAL;
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}
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ret = regmap_bulk_read(sec->m10bmc->regmap, reh_addr,
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hash, sha_num_bytes / stride);
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if (ret) {
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dev_err(dev, "failed to read root entry hash: %x cnt %x: %d\n",
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reh_addr, sha_num_bytes / stride, ret);
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return ret;
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}
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for (i = 0; i < sha_num_bytes; i++)
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cnt += sprintf(buf + cnt, "%02x", hash[i]);
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cnt += sprintf(buf + cnt, "\n");
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return cnt;
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}
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#define DEVICE_ATTR_SEC_REH_RO(_name, _magic, _prog_addr, _reh_addr) \
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static ssize_t _name##_root_entry_hash_show(struct device *dev, \
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struct device_attribute *attr, \
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char *buf) \
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{ return show_root_entry_hash(dev, _magic, _prog_addr, _reh_addr, buf); } \
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static DEVICE_ATTR_RO(_name##_root_entry_hash)
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DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR);
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DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR);
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DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR);
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#define FLASH_COUNT_SIZE 4096 /* count stored as inverted bit vector */
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static ssize_t flash_count_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct m10bmc_sec *sec = dev_get_drvdata(dev);
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unsigned int stride, num_bits;
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u8 *flash_buf;
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int cnt, ret;
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stride = regmap_get_reg_stride(sec->m10bmc->regmap);
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num_bits = FLASH_COUNT_SIZE * 8;
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flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
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if (!flash_buf)
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return -ENOMEM;
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if (FLASH_COUNT_SIZE % stride) {
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dev_err(sec->dev,
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"FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n",
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FLASH_COUNT_SIZE, stride);
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WARN_ON_ONCE(1);
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return -EINVAL;
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}
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ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
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flash_buf, FLASH_COUNT_SIZE / stride);
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if (ret) {
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dev_err(sec->dev,
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"failed to read flash count: %x cnt %x: %d\n",
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STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret);
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goto exit_free;
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}
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cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
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exit_free:
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kfree(flash_buf);
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return ret ? : sysfs_emit(buf, "%u\n", cnt);
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}
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static DEVICE_ATTR_RO(flash_count);
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static struct attribute *m10bmc_security_attrs[] = {
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&dev_attr_flash_count.attr,
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&dev_attr_bmc_root_entry_hash.attr,
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&dev_attr_sr_root_entry_hash.attr,
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&dev_attr_pr_root_entry_hash.attr,
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NULL,
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};
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static struct attribute_group m10bmc_security_attr_group = {
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.name = "security",
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.attrs = m10bmc_security_attrs,
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};
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static const struct attribute_group *m10bmc_sec_attr_groups[] = {
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&m10bmc_security_attr_group,
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NULL,
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};
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#define SEC_UPDATE_LEN_MAX 32
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static int m10bmc_sec_probe(struct platform_device *pdev)
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{
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struct m10bmc_sec *sec;
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sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
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if (!sec)
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return -ENOMEM;
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sec->dev = &pdev->dev;
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sec->m10bmc = dev_get_drvdata(pdev->dev.parent);
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dev_set_drvdata(&pdev->dev, sec);
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return 0;
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}
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static const struct platform_device_id intel_m10bmc_sec_ids[] = {
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{
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.name = "n3000bmc-sec-update",
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},
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{ }
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};
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MODULE_DEVICE_TABLE(platform, intel_m10bmc_sec_ids);
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static struct platform_driver intel_m10bmc_sec_driver = {
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.probe = m10bmc_sec_probe,
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.driver = {
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.name = "intel-m10bmc-sec-update",
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.dev_groups = m10bmc_sec_attr_groups,
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},
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.id_table = intel_m10bmc_sec_ids,
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};
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module_platform_driver(intel_m10bmc_sec_driver);
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MODULE_AUTHOR("Intel Corporation");
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MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update");
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MODULE_LICENSE("GPL");
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