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f8f6224948
Commit d35df77707 ("mtd: spi-nor: winbond: fix w25q128 regression")
upstream fixed a regression for flavors of 0xef4018 flash that don't
define SFDP tables. Add a comment on the flash definition highlighting
that there are flavors of flashes with and without SFDP support.
It spares developers searching the entire git log for when we'll better
handle these cases.
Acked-by: Pratyush Yadav <pratyush@kernel.org>
Link: https://lore.kernel.org/r/20241029080049.96679-1-tudor.ambarus@linaro.org
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
363 lines
9.7 KiB
C
363 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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#define WINBOND_NOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
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#define WINBOND_NOR_OP_WREAR 0xc5 /* Write Extended Address Register */
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#define WINBOND_NOR_WREAR_OP(buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_WREAR, 0), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(1, buf, 0))
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static int
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w25q128_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* Zetta ZD25Q128C is a clone of the Winbond device. But the encoded
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* size is really wrong. It seems that they confused Mbit with MiB.
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* Thus the flash is discovered as a 2MiB device.
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*/
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if (bfpt_header->major == SFDP_JESD216_MAJOR &&
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bfpt_header->minor == SFDP_JESD216_MINOR &&
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nor->params->size == SZ_2M &&
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nor->params->erase_map.regions[0].size == SZ_2M) {
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nor->params->size = SZ_16M;
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nor->params->erase_map.regions[0].size = SZ_16M;
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}
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return 0;
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}
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static const struct spi_nor_fixups w25q128_fixups = {
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.post_bfpt = w25q128_post_bfpt_fixups,
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};
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static int
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w25q256_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* W25Q256JV supports 4B opcodes but W25Q256FV does not.
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* Unfortunately, Winbond has re-used the same JEDEC ID for both
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* variants which prevents us from defining a new entry in the parts
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* table.
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* To differentiate between W25Q256JV and W25Q256FV check SFDP header
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* version: only JV has JESD216A compliant structure (version 5).
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*/
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if (bfpt_header->major == SFDP_JESD216_MAJOR &&
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bfpt_header->minor == SFDP_JESD216A_MINOR)
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nor->flags |= SNOR_F_4B_OPCODES;
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return 0;
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}
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static const struct spi_nor_fixups w25q256_fixups = {
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.post_bfpt = w25q256_post_bfpt_fixups,
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};
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static const struct flash_info winbond_nor_parts[] = {
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{
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.id = SNOR_ID(0xef, 0x30, 0x10),
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.name = "w25x05",
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.size = SZ_64K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x11),
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.name = "w25x10",
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.size = SZ_128K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x12),
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.name = "w25x20",
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.size = SZ_256K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x13),
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.name = "w25x40",
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.size = SZ_512K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x14),
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.name = "w25x80",
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.size = SZ_1M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x15),
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.name = "w25x16",
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.size = SZ_2M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x16),
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.name = "w25x32",
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.size = SZ_4M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x30, 0x17),
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.name = "w25x64",
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.size = SZ_8M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x12),
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.name = "w25q20cl",
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.size = SZ_256K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x14),
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.name = "w25q80bl",
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.size = SZ_1M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x16),
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.name = "w25q32",
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.size = SZ_4M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x17),
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.name = "w25q64",
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.size = SZ_8M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x18),
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/* Flavors w/ and w/o SFDP. */
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.name = "w25q128",
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.size = SZ_16M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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.fixups = &w25q128_fixups,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x19),
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.name = "w25q256",
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.size = SZ_32M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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.fixups = &w25q256_fixups,
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}, {
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.id = SNOR_ID(0xef, 0x40, 0x20),
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.name = "w25q512jvq",
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.size = SZ_64M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x50, 0x12),
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.name = "w25q20bw",
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.size = SZ_256K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x50, 0x14),
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.name = "w25q80",
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.size = SZ_1M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x12),
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.name = "w25q20ew",
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.size = SZ_256K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x15),
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.name = "w25q16dw",
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.size = SZ_2M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x16),
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.name = "w25q32dw",
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.size = SZ_4M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x17),
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.name = "w25q64dw",
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.size = SZ_8M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x18),
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.name = "w25q128fw",
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.size = SZ_16M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x19),
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.name = "w25q256jw",
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.size = SZ_32M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x60, 0x20),
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.name = "w25q512nwq",
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.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
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}, {
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.id = SNOR_ID(0xef, 0x70, 0x15),
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.name = "w25q16jv-im/jm",
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.size = SZ_2M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x70, 0x16),
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.name = "w25q32jv",
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.size = SZ_4M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x70, 0x17),
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.name = "w25q64jvm",
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.size = SZ_8M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0xef, 0x70, 0x18),
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.name = "w25q128jv",
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.size = SZ_16M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x70, 0x19),
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.name = "w25q256jvm",
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}, {
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.id = SNOR_ID(0xef, 0x71, 0x19),
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.name = "w25m512jv",
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.size = SZ_64M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x80, 0x16),
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.name = "w25q32jwm",
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.size = SZ_4M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
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}, {
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.id = SNOR_ID(0xef, 0x80, 0x17),
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.name = "w25q64jwm",
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.size = SZ_8M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x80, 0x18),
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.name = "w25q128jwm",
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.size = SZ_16M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x80, 0x19),
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.name = "w25q256jwm",
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.size = SZ_32M,
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.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0xef, 0x80, 0x20),
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.name = "w25q512nwm",
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.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
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},
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};
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/**
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* winbond_nor_write_ear() - Write Extended Address Register.
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* @nor: pointer to 'struct spi_nor'.
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* @ear: value to write to the Extended Address Register.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int winbond_nor_write_ear(struct spi_nor *nor, u8 ear)
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{
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int ret;
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nor->bouncebuf[0] = ear;
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if (nor->spimem) {
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struct spi_mem_op op = WINBOND_NOR_WREAR_OP(nor->bouncebuf);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_write_reg(nor,
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WINBOND_NOR_OP_WREAR,
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nor->bouncebuf, 1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d writing EAR\n", ret);
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return ret;
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}
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/**
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* winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winbond
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* flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int winbond_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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{
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int ret;
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ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable);
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if (ret || enable)
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return ret;
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/*
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* On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
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* Register to be set to 1, so all 3-byte-address reads come from the
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* second 16M. We must clear the register to enable normal behavior.
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*/
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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ret = winbond_nor_write_ear(nor, 0);
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if (ret)
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return ret;
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return spi_nor_write_disable(nor);
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}
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static const struct spi_nor_otp_ops winbond_nor_otp_ops = {
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.read = spi_nor_otp_read_secr,
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.write = spi_nor_otp_write_secr,
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.erase = spi_nor_otp_erase_secr,
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.lock = spi_nor_otp_lock_sr2,
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.is_locked = spi_nor_otp_is_locked_sr2,
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};
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static int winbond_nor_late_init(struct spi_nor *nor)
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{
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struct spi_nor_flash_parameter *params = nor->params;
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if (params->otp.org)
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params->otp.ops = &winbond_nor_otp_ops;
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/*
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* Winbond seems to require that the Extended Address Register to be set
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* to zero when exiting the 4-Byte Address Mode, at least for W25Q256FV.
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* This requirement is not described in the JESD216 SFDP standard, thus
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* it is Winbond specific. Since we do not know if other Winbond flashes
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* have the same requirement, play safe and overwrite the method parsed
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* from BFPT, if any.
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*/
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params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode;
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return 0;
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}
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static const struct spi_nor_fixups winbond_nor_fixups = {
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.late_init = winbond_nor_late_init,
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};
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const struct spi_nor_manufacturer spi_nor_winbond = {
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.name = "winbond",
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.parts = winbond_nor_parts,
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.nparts = ARRAY_SIZE(winbond_nor_parts),
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.fixups = &winbond_nor_fixups,
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};
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