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2f50304e9e
Add serial support for RZ/V2H(P) SoC with earlycon. The SCIF interface in the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L (R9A07G044) SoC, with the following differences: - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready and two for Rx and Tx buffer full, all of which are edge-triggered. - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both synchronous and asynchronous modes. - There are differences in the configuration of certain registers such as SCSMR, SCFCR, and SCSPTR between the two SoCs. To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE is added. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240604170513.522631-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SERIAL_SCI_H
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#define __LINUX_SERIAL_SCI_H
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#include <linux/bitops.h>
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#include <linux/serial_core.h>
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#include <linux/sh_dma.h>
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/*
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* Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
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*/
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/* Serial Control Register (@ = not supported by all parts) */
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#define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */
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#define SCSCR_TE BIT(5) /* Transmit Enable */
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#define SCSCR_RE BIT(4) /* Receive Enable */
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#define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable @ */
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#define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable @ */
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#define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */
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#define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */
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enum {
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SCIx_PROBE_REGTYPE,
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SCIx_SCI_REGTYPE,
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SCIx_IRDA_REGTYPE,
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SCIx_SCIFA_REGTYPE,
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SCIx_SCIFB_REGTYPE,
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SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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SCIx_SH3_SCIF_REGTYPE,
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SCIx_SH4_SCIF_REGTYPE,
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SCIx_SH4_SCIF_BRG_REGTYPE,
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SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
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SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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SCIx_SH7705_SCIF_REGTYPE,
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SCIx_HSCIF_REGTYPE,
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SCIx_RZ_SCIFA_REGTYPE,
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SCIx_RZV2H_SCIF_REGTYPE,
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SCIx_NR_REGTYPES,
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};
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struct plat_sci_port_ops {
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void (*init_pins)(struct uart_port *, unsigned int cflag);
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};
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/*
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* Platform device specific platform_data struct
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*/
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struct plat_sci_port {
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unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
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upf_t flags; /* UPF_* flags */
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unsigned int sampling_rate;
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unsigned int scscr; /* SCSCR initialization */
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/*
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* Platform overrides if necessary, defaults otherwise.
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*/
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unsigned char regtype;
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struct plat_sci_port_ops *ops;
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};
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#endif /* __LINUX_SERIAL_SCI_H */
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