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3e28d37146
Introduce i915_sched_engine object which is lower level data structure that i915_scheduler / generic code can operate on without touching execlist specific structures. This allows additional submission backends to be added without breaking the layering. Currently the execlists backend uses 1 of these object per each engine (physical or virtual) but future backends like the GuC will point to less instances utilizing the reference counting. This is a bit of detour to integrating the i915 with the DRM scheduler but this object will still exist when the DRM scheduler lands in the i915. It will however look a bit different. It will encapsulate the drm_gpu_scheduler object plus and common variables (to the backends) related to scheduling. Regardless this is a step in the right direction. This patch starts the aforementioned transition by moving the priolist into the i915_sched_engine object. v3: (Jason Ekstrand) Update comment next to intel_engine_cs.virtual Add kernel doc (Checkpatch) Fix double the in commit message v4: (Daniele) Update comment message. Add comment about subclass field Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210618010638.98941-2-matthew.brost@intel.com |
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| .. | ||
| bridge | ||
| dp-mst | ||
| rfc | ||
| afbc.rst | ||
| amdgpu-dc.rst | ||
| amdgpu.rst | ||
| backlight.rst | ||
| driver-uapi.rst | ||
| drivers.rst | ||
| drm-client.rst | ||
| drm-internals.rst | ||
| drm-kms-helpers.rst | ||
| drm-kms.rst | ||
| drm-mm.rst | ||
| drm-uapi.rst | ||
| i915.rst | ||
| index.rst | ||
| introduction.rst | ||
| kms-properties.csv | ||
| komeda-kms.rst | ||
| mcde.rst | ||
| meson.rst | ||
| msm-crash-dump.rst | ||
| pl111.rst | ||
| tegra.rst | ||
| todo.rst | ||
| tve200.rst | ||
| v3d.rst | ||
| vc4.rst | ||
| vga-switcheroo.rst | ||
| vgaarbiter.rst | ||
| vkms.rst | ||
| xen-front.rst | ||