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b34ae8598c
On SM8550, two sets of UFS PHY settings are provided, one set is to support HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY settings are programming different values to different registers, mixing the two sets and/or overwriting one set with another set is definitely not blessed by UFS PHY designers. To add HS-G5 support for SM8550, split the two sets of PHY settings into their dedicated overlay tables, only the common parts of the two sets of PHY settings are left in the .tbls. Consider we are going to add even higher gear support in future, to avoid adding more tables with different names, rename the .tbls_hs_g4 and make it an array, a size of 2 is enough as of now. In this case, .tbls alone is not a complete set of PHY settings, so either tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the .tbls to become a complete set of PHY settings. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Can Guo <quic_cang@quicinc.com> Link: https://lore.kernel.org/r/1703557892-1822-1-git-send-email-quic_cang@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
47 lines
1.9 KiB
C
47 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
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#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
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#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
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#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
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#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58
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#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4
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#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
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#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
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#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
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#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
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#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
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#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
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#define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0
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#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
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#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
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#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
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#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
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#endif
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