Chunyan Zhang 497b59565b Coresight: ETMv4: Prevent TRCRSCTLR0&1 from being accessed ...

1. TRCRSCTLRn - Resource Selection Control Registers n=0~1 are reserved,
   we shouldn't access them.
2. The max number of 'n' here is defined in TRCIDR4.NUMRSPAIR whoes value
   indicates the number of resource selection *pairs*, and 0 indicates
   one resource selection pair, 1 indicates two pairs, and so on ...

So, the total number of resource selection control registers which we can
access is (TRCIDR4.NUMRSPAIR * 2)

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2015-10-07 17:54:09 +01:00

..

coresight

Coresight: ETMv4: Prevent TRCRSCTLR0&1 from being accessed

2015-10-07 17:54:09 +01:00

intel_th

intel_th: Add PTI output driver

2015-10-04 20:28:58 +01:00

stm

stm class: stm_console: Add kernel-console-over-stm driver

2015-10-04 20:28:58 +01:00