Dan Williams 5f653f7590 cxl/core: Rename bus.c to core.c ... In preparation for more generic shared functionality across endpoint consumers of core cxl resources, and platform-firmware producers of those resources, rename bus.c to core.c. In addition to the central rendezvous for interleave coordination, the core will also define common routines like CXL register block mapping. Acked-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162096972018.1865304.11079951161445408423.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2021-05-14 16:13:19 -07:00
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index.rst	cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints	2021-02-16 20:36:38 -08:00
memory-devices.rst	cxl/core: Rename bus.c to core.c	2021-05-14 16:13:19 -07:00