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6a9eda3441
Some of Infineon SPI NOR flash devices support hybrid sector layout that overlays 4KB sectors on a 256KB sector and SPI NOR framework recognizes that by parsing SMPT and construct params->erase_map. The hybrid sector layout is similar to CFI flash devices that have small sectors on top and/or bottom address. In case of CFI flash devices, the erase map information is parsed through CFI table and populated into mtd->eraseregions so that users can create MTD partitions that aligned with small sector boundaries. This patch provides the same capability to SPI NOR flash devices that have non-uniform erase map. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/35d0962986e493b06c13bdf7ada8130a9966dc02.1708404584.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> |
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.. | ||
controllers | ||
atmel.c | ||
core.c | ||
core.h | ||
debugfs.c | ||
eon.c | ||
esmt.c | ||
everspin.c | ||
gigadevice.c | ||
intel.c | ||
issi.c | ||
Kconfig | ||
macronix.c | ||
Makefile | ||
micron-st.c | ||
otp.c | ||
sfdp.c | ||
sfdp.h | ||
spansion.c | ||
sst.c | ||
swp.c | ||
sysfs.c | ||
winbond.c | ||
xilinx.c | ||
xmc.c |