CMU_TOP is the top level clock management unit which contains PLLs, muxes,
dividers and gates that feed the other clock management units.
CMU_PERIS provides clocks for GIC and MCT
CMU_FSYS0 provides clocks for USBDRD30
CMU_FSYS1 provides clocks for MMC, UFS and PCIE
CMU_PERIC0 provides clocks for UART_DBG, USI00 ~ USI03
CMU_PERIC1 provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13,
HSI2C_CAM0/1/2/3
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023090136.537395-4-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
9174fac3b3