Conor Dooley 9291e7f6f9 dt-bindings: riscv: fix single letter canonical order ... commit a943385aa8 upstream. I used the wikipedia table for ordering extensions when updating the pattern here in commit 299824e68b ("dt-bindings: riscv: add new riscv,isa strings for emulators"). Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68b ("dt-bindings: riscv: add new riscv,isa strings for emulators") Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221205174459.60195-3-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2023-02-01 08:34:50 +01:00
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canaan.yaml	dt-bindings: add Canaan boards compatible strings	2021-02-22 17:51:06 -08:00
cpus.yaml	dt-bindings: riscv: fix single letter canonical order	2023-02-01 08:34:50 +01:00
microchip.yaml	RISC-V Patches for the 6.1 Merge Window, Part 2	2022-10-14 11:21:11 -07:00
sifive,ccache0.yaml	dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache	2022-10-13 11:06:50 -07:00
sifive.yaml	dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board	2021-01-07 17:37:41 -08:00
starfive.yaml	dt-bindings: riscv: add starfive jh7100 bindings	2021-08-04 13:25:28 -07:00