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78341049fb
As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under normal operation, the device should be operated in PLCA mode. Disabling collision detection is recommended to allow the device to operate in noisy environments or when reflections and other inherent transmission line distortion cause poor signal quality. Collision detection must be re-enabled if the device is configured to operate in CSMA/CD mode. Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-8-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
513 lines
14 KiB
C
513 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Microchip 10BASE-T1S PHYs
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*
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* Support: Microchip Phys:
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* lan8670/1/2 Rev.B1/C1/C2
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* lan8650/1 Rev.B0/B1 Internal PHYs
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#define PHY_ID_LAN867X_REVB1 0x0007C162
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#define PHY_ID_LAN867X_REVC1 0x0007C164
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#define PHY_ID_LAN867X_REVC2 0x0007C165
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/* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */
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#define PHY_ID_LAN865X_REVB 0x0007C1B3
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#define LAN867X_REG_STS2 0x0019
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#define LAN867x_RESET_COMPLETE_STS BIT(11)
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#define LAN865X_REG_CFGPARAM_ADDR 0x00D8
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#define LAN865X_REG_CFGPARAM_DATA 0x00D9
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#define LAN865X_REG_CFGPARAM_CTRL 0x00DA
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#define LAN865X_REG_STS2 0x0019
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/* Collision Detector Control 0 Register */
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#define LAN86XX_REG_COL_DET_CTRL0 0x0087
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#define COL_DET_CTRL0_ENABLE_BIT_MASK BIT(15)
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#define COL_DET_ENABLE BIT(15)
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#define COL_DET_DISABLE 0x0000
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#define LAN865X_CFGPARAM_READ_ENABLE BIT(1)
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/* The arrays below are pulled from the following table from AN1699
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* Access MMD Address Value Mask
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* RMW 0x1F 0x00D0 0x0002 0x0E03
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* RMW 0x1F 0x00D1 0x0000 0x0300
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* RMW 0x1F 0x0084 0x3380 0xFFC0
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* RMW 0x1F 0x0085 0x0006 0x000F
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* RMW 0x1F 0x008A 0xC000 0xF800
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* RMW 0x1F 0x0087 0x801C 0x801C
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* RMW 0x1F 0x0088 0x033F 0x1FFF
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* W 0x1F 0x008B 0x0404 ------
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* RMW 0x1F 0x0080 0x0600 0x0600
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* RMW 0x1F 0x00F1 0x2400 0x7F00
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* RMW 0x1F 0x0096 0x2000 0x2000
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* W 0x1F 0x0099 0x7F80 ------
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*/
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static const u32 lan867x_revb1_fixup_registers[12] = {
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0x00D0, 0x00D1, 0x0084, 0x0085,
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0x008A, 0x0087, 0x0088, 0x008B,
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0x0080, 0x00F1, 0x0096, 0x0099,
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};
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static const u16 lan867x_revb1_fixup_values[12] = {
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0x0002, 0x0000, 0x3380, 0x0006,
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0xC000, 0x801C, 0x033F, 0x0404,
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0x0600, 0x2400, 0x2000, 0x7F80,
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};
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static const u16 lan867x_revb1_fixup_masks[12] = {
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0x0E03, 0x0300, 0xFFC0, 0x000F,
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0xF800, 0x801C, 0x1FFF, 0xFFFF,
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0x0600, 0x7F00, 0x2000, 0xFFFF,
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};
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/* LAN865x Rev.B0/B1 configuration parameters from AN1760
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* As per the Configuration Application Note AN1760 published in the below link,
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* https://www.microchip.com/en-us/application-notes/an1760
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* Revision F (DS60001760G - June 2024)
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*/
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static const u32 lan865x_revb_fixup_registers[17] = {
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0x00D0, 0x00E0, 0x00E9, 0x00F5,
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0x00F4, 0x00F8, 0x00F9, 0x0081,
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0x0091, 0x0043, 0x0044, 0x0045,
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0x0053, 0x0054, 0x0055, 0x0040,
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0x0050,
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};
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static const u16 lan865x_revb_fixup_values[17] = {
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0x3F31, 0xC000, 0x9E50, 0x1CF8,
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0xC020, 0xB900, 0x4E53, 0x0080,
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0x9660, 0x00FF, 0xFFFF, 0x0000,
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0x00FF, 0xFFFF, 0x0000, 0x0002,
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0x0002,
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};
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static const u16 lan865x_revb_fixup_cfg_regs[2] = {
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0x0084, 0x008A,
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};
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static const u32 lan865x_revb_sqi_fixup_regs[12] = {
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0x00B0, 0x00B1, 0x00B2, 0x00B3,
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0x00B4, 0x00B5, 0x00B6, 0x00B7,
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0x00B8, 0x00B9, 0x00BA, 0x00BB,
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};
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static const u16 lan865x_revb_sqi_fixup_values[12] = {
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0x0103, 0x0910, 0x1D26, 0x002A,
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0x0103, 0x070D, 0x1720, 0x0027,
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0x0509, 0x0E13, 0x1C25, 0x002B,
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};
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static const u16 lan865x_revb_sqi_fixup_cfg_regs[3] = {
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0x00AD, 0x00AE, 0x00AF,
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};
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/* Pulled from AN1760 describing 'indirect read'
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*
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* write_register(0x4, 0x00D8, addr)
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* write_register(0x4, 0x00DA, 0x2)
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* return (int8)(read_register(0x4, 0x00D9))
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*
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* 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2
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*/
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static int lan865x_revb_indirect_read(struct phy_device *phydev, u16 addr)
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{
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int ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR,
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addr);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL,
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LAN865X_CFGPARAM_READ_ENABLE);
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if (ret)
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return ret;
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return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA);
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}
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/* This is pulled straight from AN1760 from 'calculation of offset 1' &
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* 'calculation of offset 2'
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*/
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static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[])
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{
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const u16 fixup_regs[2] = {0x0004, 0x0008};
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int ret;
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for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) {
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ret = lan865x_revb_indirect_read(phydev, fixup_regs[i]);
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if (ret < 0)
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return ret;
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/* 5-bit signed value, sign extend */
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ret &= GENMASK(4, 0);
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if (ret & BIT(4))
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offsets[i] = ret | 0xE0;
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else
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offsets[i] = ret;
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}
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return 0;
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}
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static int lan865x_read_cfg_params(struct phy_device *phydev,
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const u16 cfg_regs[], u16 cfg_params[],
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u8 count)
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{
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int ret;
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for (int i = 0; i < count; i++) {
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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cfg_regs[i]);
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if (ret < 0)
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return ret;
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cfg_params[i] = (u16)ret;
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}
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return 0;
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}
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static int lan865x_write_cfg_params(struct phy_device *phydev,
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const u16 cfg_regs[], u16 cfg_params[],
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u8 count)
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{
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int ret;
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for (int i = 0; i < count; i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i],
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cfg_params[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[])
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{
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u16 cfg_results[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)];
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u16 cfg_params[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)];
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int ret;
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ret = lan865x_read_cfg_params(phydev, lan865x_revb_fixup_cfg_regs,
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cfg_params, ARRAY_SIZE(cfg_params));
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if (ret)
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return ret;
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cfg_results[0] = FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |
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FIELD_PREP(GENMASK(9, 4), 14 + offsets[0]) |
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0x03;
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cfg_results[1] = FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]);
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return lan865x_write_cfg_params(phydev, lan865x_revb_fixup_cfg_regs,
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cfg_results, ARRAY_SIZE(cfg_results));
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}
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static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[])
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{
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u16 cfg_results[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)];
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u16 cfg_params[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)];
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int ret;
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ret = lan865x_read_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs,
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cfg_params, ARRAY_SIZE(cfg_params));
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if (ret)
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return ret;
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cfg_results[0] = FIELD_PREP(GENMASK(13, 8), 5 + offsets[0]) |
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(9 + offsets[0]);
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cfg_results[1] = FIELD_PREP(GENMASK(13, 8), 9 + offsets[0]) |
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(14 + offsets[0]);
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cfg_results[2] = FIELD_PREP(GENMASK(13, 8), 17 + offsets[0]) |
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(22 + offsets[0]);
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return lan865x_write_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs,
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cfg_results, ARRAY_SIZE(cfg_results));
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}
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static int lan865x_revb_config_init(struct phy_device *phydev)
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{
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s8 offsets[2];
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int ret;
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/* Reference to AN1760
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* https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.pdf
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*/
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ret = lan865x_generate_cfg_offsets(phydev, offsets);
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if (ret)
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return ret;
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for (int i = 0; i < ARRAY_SIZE(lan865x_revb_fixup_registers); i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb_fixup_registers[i],
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lan865x_revb_fixup_values[i]);
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if (ret)
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return ret;
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if (i == 1) {
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ret = lan865x_setup_cfgparam(phydev, offsets);
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if (ret)
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return ret;
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}
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}
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ret = lan865x_setup_sqi_cfgparam(phydev, offsets);
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if (ret)
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return ret;
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for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb_sqi_fixup_regs[i],
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lan865x_revb_sqi_fixup_values[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int lan867x_check_reset_complete(struct phy_device *phydev)
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{
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int err;
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/* The chip completes a reset in 3us, we might get here earlier than
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* that, as an added margin we'll conditionally sleep 5us.
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*/
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err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2);
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if (err < 0)
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return err;
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if (!(err & LAN867x_RESET_COMPLETE_STS)) {
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udelay(5);
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err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2);
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if (err < 0)
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return err;
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if (!(err & LAN867x_RESET_COMPLETE_STS)) {
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phydev_err(phydev, "PHY reset failed\n");
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return -ENODEV;
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}
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}
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return 0;
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}
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static int lan867x_revc_config_init(struct phy_device *phydev)
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{
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s8 offsets[2];
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int ret;
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ret = lan867x_check_reset_complete(phydev);
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if (ret)
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return ret;
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ret = lan865x_generate_cfg_offsets(phydev, offsets);
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if (ret)
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return ret;
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/* LAN867x Rev.C1/C2 configuration settings are equal to the first 9
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* configuration settings and all the sqi fixup settings from LAN865x
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* Rev.B0/B1. So the same fixup registers and values from LAN865x
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* Rev.B0/B1 are used for LAN867x Rev.C1/C2 to avoid duplication.
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* Refer the below links for the comparison.
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* https://www.microchip.com/en-us/application-notes/an1760
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* Revision F (DS60001760G - June 2024)
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* https://www.microchip.com/en-us/application-notes/an1699
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* Revision E (DS60001699F - June 2024)
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*/
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for (int i = 0; i < 9; i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb_fixup_registers[i],
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lan865x_revb_fixup_values[i]);
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if (ret)
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return ret;
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if (i == 1) {
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ret = lan865x_setup_cfgparam(phydev, offsets);
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if (ret)
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return ret;
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}
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}
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ret = lan865x_setup_sqi_cfgparam(phydev, offsets);
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if (ret)
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return ret;
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for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb_sqi_fixup_regs[i],
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lan865x_revb_sqi_fixup_values[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int lan867x_revb1_config_init(struct phy_device *phydev)
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{
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int err;
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err = lan867x_check_reset_complete(phydev);
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if (err)
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return err;
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/* Reference to AN1699
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* https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf
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* AN1699 says Read, Modify, Write, but the Write is not required if the
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* register already has the required value. So it is safe to use
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* phy_modify_mmd here.
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*/
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for (int i = 0; i < ARRAY_SIZE(lan867x_revb1_fixup_registers); i++) {
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err = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
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lan867x_revb1_fixup_registers[i],
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lan867x_revb1_fixup_masks[i],
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lan867x_revb1_fixup_values[i]);
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if (err)
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return err;
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}
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return 0;
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}
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/* As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and
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* LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under
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* normal operation, the device should be operated in PLCA mode. Disabling
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* collision detection is recommended to allow the device to operate in noisy
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* environments or when reflections and other inherent transmission line
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* distortion cause poor signal quality. Collision detection must be re-enabled
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* if the device is configured to operate in CSMA/CD mode.
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*
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* AN1760: https://www.microchip.com/en-us/application-notes/an1760
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* AN1699: https://www.microchip.com/en-us/application-notes/an1699
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*/
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static int lan86xx_plca_set_cfg(struct phy_device *phydev,
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const struct phy_plca_cfg *plca_cfg)
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{
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int ret;
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ret = genphy_c45_plca_set_cfg(phydev, plca_cfg);
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if (ret)
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return ret;
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if (plca_cfg->enabled)
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return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
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LAN86XX_REG_COL_DET_CTRL0,
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COL_DET_CTRL0_ENABLE_BIT_MASK,
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COL_DET_DISABLE);
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return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0,
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COL_DET_CTRL0_ENABLE_BIT_MASK, COL_DET_ENABLE);
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}
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static int lan86xx_read_status(struct phy_device *phydev)
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{
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/* The phy has some limitations, namely:
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* - always reports link up
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* - only supports 10MBit half duplex
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* - does not support auto negotiate
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*/
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phydev->link = 1;
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phydev->duplex = DUPLEX_HALF;
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phydev->speed = SPEED_10;
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phydev->autoneg = AUTONEG_DISABLE;
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return 0;
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}
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/* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and
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* C45 registers space. If the PHY is discovered via C22 bus protocol it assumes
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* it uses C22 protocol and always uses C22 registers indirect access to access
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* C45 registers. This is because, we don't have a clean separation between
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* C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C45
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* registers direct access can't be used which can save multiple SPI bus access.
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* To support this feature, set .read_mmd/.write_mmd in the PHY driver to call
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* .read_c45/.write_c45 in the OPEN Alliance framework
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* drivers/net/ethernet/oa_tc6.c
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*/
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static int lan865x_phy_read_mmd(struct phy_device *phydev, int devnum,
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u16 regnum)
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{
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struct mii_bus *bus = phydev->mdio.bus;
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int addr = phydev->mdio.addr;
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return __mdiobus_c45_read(bus, addr, devnum, regnum);
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}
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static int lan865x_phy_write_mmd(struct phy_device *phydev, int devnum,
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u16 regnum, u16 val)
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{
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struct mii_bus *bus = phydev->mdio.bus;
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int addr = phydev->mdio.addr;
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return __mdiobus_c45_write(bus, addr, devnum, regnum, val);
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}
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static struct phy_driver microchip_t1s_driver[] = {
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{
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PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1),
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.name = "LAN867X Rev.B1",
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.features = PHY_BASIC_T1S_P2MP_FEATURES,
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.config_init = lan867x_revb1_config_init,
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.read_status = lan86xx_read_status,
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.get_plca_cfg = genphy_c45_plca_get_cfg,
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.set_plca_cfg = genphy_c45_plca_set_cfg,
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.get_plca_status = genphy_c45_plca_get_status,
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},
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{
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PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1),
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.name = "LAN867X Rev.C1",
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.features = PHY_BASIC_T1S_P2MP_FEATURES,
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.config_init = lan867x_revc_config_init,
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.read_status = lan86xx_read_status,
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.get_plca_cfg = genphy_c45_plca_get_cfg,
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.set_plca_cfg = lan86xx_plca_set_cfg,
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.get_plca_status = genphy_c45_plca_get_status,
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},
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{
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PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2),
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.name = "LAN867X Rev.C2",
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.features = PHY_BASIC_T1S_P2MP_FEATURES,
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.config_init = lan867x_revc_config_init,
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.read_status = lan86xx_read_status,
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.get_plca_cfg = genphy_c45_plca_get_cfg,
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.set_plca_cfg = lan86xx_plca_set_cfg,
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.get_plca_status = genphy_c45_plca_get_status,
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},
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{
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PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB),
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.name = "LAN865X Rev.B0/B1 Internal Phy",
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.features = PHY_BASIC_T1S_P2MP_FEATURES,
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.config_init = lan865x_revb_config_init,
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.read_status = lan86xx_read_status,
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.read_mmd = lan865x_phy_read_mmd,
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.write_mmd = lan865x_phy_write_mmd,
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.get_plca_cfg = genphy_c45_plca_get_cfg,
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.set_plca_cfg = lan86xx_plca_set_cfg,
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.get_plca_status = genphy_c45_plca_get_status,
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},
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};
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module_phy_driver(microchip_t1s_driver);
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static struct mdio_device_id __maybe_unused tbl[] = {
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{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, tbl);
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MODULE_DESCRIPTION("Microchip 10BASE-T1S PHYs driver");
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MODULE_AUTHOR("Ramón Nordin Rodriguez");
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MODULE_LICENSE("GPL");
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