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According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5: The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C transfer. But maximum stall time is 100us. The IRQs have to be disabled to prevent schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if any irq or schedule happen during transaction. Replace mutex with spin_lock_irqsave() to avoid stalling SCL more than 100us. Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20241002-svc-i3c-hj-v6-4-7e6e1d3569ae@nxp.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> |
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internals.h | ||
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master.c |