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f64c146410
- fix use-before-set error in ibmphp (Dan Carpenter)
- fix pciehp timeouts caused by Command Completed errata (Bjorn Helgaas)
- fix refcounting in pnv_php hotplug (Julia Lawall)
- clear pciehp Presence Detect and Data Link Layer Status Changed on
resume so we don't miss hotplug events (Mika Westerberg)
- only request pciehp control if we support it, so platform can use ACPI
hotplug otherwise (Mika Westerberg)
- convert SHPC to be builtin only (Mika Westerberg)
- request SHPC control via _OSC if we support it (Mika Westerberg)
- simplify SHPC handoff from firmware (Mika Westerberg)
* pci/hotplug:
PCI: Improve "partially hidden behind bridge" log message
PCI: Improve pci_scan_bridge() and pci_scan_bridge_extend() doc
PCI: Move resource distribution for single bridge outside loop
PCI: Account for all bridges on bus when distributing bus numbers
ACPI / hotplug / PCI: Drop unnecessary parentheses
ACPI / hotplug / PCI: Mark stale PCI devices disconnected
ACPI / hotplug / PCI: Don't scan bridges managed by native hotplug
PCI: hotplug: Add hotplug_is_native()
PCI: shpchp: Add shpchp_is_native()
PCI: shpchp: Fix AMD POGO identification
PCI: shpchp: Use dev_printk() for OSHP-related messages
PCI: shpchp: Remove get_hp_hw_control_from_firmware() wrapper
PCI: shpchp: Remove acpi_get_hp_hw_control_from_firmware() flags
PCI: shpchp: Rely on previous _OSC results
PCI: shpchp: Request SHPC control via _OSC when adding host bridge
PCI: shpchp: Convert SHPC to be builtin only
PCI: pciehp: Make pciehp_is_native() stricter
PCI: pciehp: Rename host->native_hotplug to host->native_pcie_hotplug
PCI: pciehp: Request control of native hotplug only if supported
PCI: pciehp: Clear Presence Detect and Data Link Layer Status Changed on resume
PCI: pnv_php: Add missing of_node_put()
PCI: pciehp: Add quirk for Command Completed errata
PCI: Add Qualcomm vendor ID
PCI: ibmphp: Fix use-before-set in get_max_bus_speed()
# Conflicts:
# drivers/acpi/pci_root.c
117 lines
3.6 KiB
C
117 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Purpose: PCI Express Port Bus Driver's Internal Data Structures
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef _PORTDRV_H_
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#define _PORTDRV_H_
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#include <linux/compiler.h>
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/* Service Type */
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#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
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#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
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#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
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#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
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#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
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#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
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#define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
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#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
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#define PCIE_PORT_DEVICE_MAXSERVICES 4
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/* Port Type */
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#define PCIE_ANY_PORT (~0)
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struct pcie_device {
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int irq; /* Service IRQ/MSI/MSI-X Vector */
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struct pci_dev *port; /* Root/Upstream/Downstream Port */
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u32 service; /* Port service this device represents */
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void *priv_data; /* Service Private Data */
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struct device device; /* Generic Device Interface */
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};
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#define to_pcie_device(d) container_of(d, struct pcie_device, device)
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static inline void set_service_data(struct pcie_device *dev, void *data)
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{
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dev->priv_data = data;
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}
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static inline void *get_service_data(struct pcie_device *dev)
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{
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return dev->priv_data;
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}
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struct pcie_port_service_driver {
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const char *name;
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int (*probe) (struct pcie_device *dev);
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void (*remove) (struct pcie_device *dev);
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int (*suspend) (struct pcie_device *dev);
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int (*resume) (struct pcie_device *dev);
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/* Device driver may resume normal operations */
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void (*error_resume)(struct pci_dev *dev);
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/* Link Reset Capability - AER service driver specific */
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pci_ers_result_t (*reset_link) (struct pci_dev *dev);
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int port_type; /* Type of the port this driver can handle */
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u32 service; /* Port service this device represents */
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struct device_driver driver;
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};
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#define to_service_driver(d) \
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container_of(d, struct pcie_port_service_driver, driver)
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int pcie_port_service_register(struct pcie_port_service_driver *new);
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void pcie_port_service_unregister(struct pcie_port_service_driver *new);
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/*
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* The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
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* be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
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* supports a maximum of 32 vectors per function.
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*/
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#define PCIE_PORT_MAX_MSI_ENTRIES 32
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#define get_descriptor_id(type, service) (((type - 4) << 8) | service)
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extern struct bus_type pcie_port_bus_type;
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int pcie_port_device_register(struct pci_dev *dev);
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#ifdef CONFIG_PM
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int pcie_port_device_suspend(struct device *dev);
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int pcie_port_device_resume(struct device *dev);
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#endif
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void pcie_port_device_remove(struct pci_dev *dev);
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int __must_check pcie_port_bus_register(void);
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void pcie_port_bus_unregister(void);
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struct pci_dev;
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#ifdef CONFIG_PCIE_PME
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extern bool pcie_pme_msi_disabled;
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static inline void pcie_pme_disable_msi(void)
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{
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pcie_pme_msi_disabled = true;
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}
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static inline bool pcie_pme_no_msi(void)
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{
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return pcie_pme_msi_disabled;
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}
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void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
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#else /* !CONFIG_PCIE_PME */
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static inline void pcie_pme_disable_msi(void) {}
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static inline bool pcie_pme_no_msi(void) { return false; }
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static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
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#endif /* !CONFIG_PCIE_PME */
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struct pcie_port_service_driver *pcie_port_find_service(struct pci_dev *dev,
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u32 service);
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struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
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#endif /* _PORTDRV_H_ */
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