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TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), however MIPI DSI output only seems to work when PLL_MIPI is selected and thus the choice must be hardcoded in. Currently, this driver can't propagate rate change from N-K-M clocks (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating in setting of the TCON0 data clock rate, limiting the precision with which a target pixel clock can be matched. For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock can deviate up to 8% off target. Signed-off-by: Roman Beranek <me@crly.cz> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20230505052110.67514-2-me@crly.cz Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>