2019-06-04 10:11:33 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2011-06-06 17:56:49 +05:30
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/*
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* omap-secure.h: OMAP Secure infrastructure header.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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2013-09-18 21:43:56 +02:00
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* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
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2020-04-10 14:34:00 -07:00
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* Copyright (C) 2013 Pali Rohár <pali@kernel.org>
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2011-06-06 17:56:49 +05:30
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*/
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#ifndef OMAP_ARCH_OMAP_SECURE_H
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#define OMAP_ARCH_OMAP_SECURE_H
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2020-01-02 16:19:41 -05:00
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#include <linux/types.h>
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2011-06-06 17:56:49 +05:30
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/* Monitor error code */
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#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
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#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
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/* HAL API error codes */
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#define API_HAL_RET_VALUE_OK 0x00
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#define API_HAL_RET_VALUE_FAIL 0x01
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/* Secure HAL API flags */
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#define FLAG_START_CRITICAL 0x4
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#define FLAG_IRQFIQ_MASK 0x3
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#define FLAG_IRQ_ENABLE 0x2
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#define FLAG_FIQ_ENABLE 0x1
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#define NO_FLAG 0x0
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2011-06-06 20:28:23 +05:30
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/* Maximum Secure memory storage size */
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#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
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2011-06-06 17:56:49 +05:30
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2017-11-27 08:57:26 -08:00
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#define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
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2011-06-06 17:56:49 +05:30
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/* Secure low power HAL API index */
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#define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a
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#define OMAP4_HAL_SAVEHW_INDEX 0x1b
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#define OMAP4_HAL_SAVEALL_INDEX 0x1c
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#define OMAP4_HAL_SAVEGIC_INDEX 0x1d
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2010-06-16 22:19:48 +05:30
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/* Secure Monitor mode APIs */
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#define OMAP4_MON_SCU_PWR_INDEX 0x108
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2011-01-09 02:59:09 +05:30
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#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
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#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
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#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
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#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
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2010-06-16 22:19:48 +05:30
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2013-10-10 13:13:48 +05:30
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#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
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2013-02-08 17:07:31 +05:30
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#define OMAP5_MON_AMBA_IF_INDEX 0x108
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ARM: OMAP5 / DRA7: Introduce workaround for 801819
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Note: the configuration for the workaround needs to be done with
each CPU bringup, since CPU0 bringup is done by bootloader, it is
recommended to have the workaround in the bootloader, kernel also does
ensure that CPU0 has the workaround and makes the workaround active
when CPU1 gets active.
With CONFIG_SMP disabled, it is expected to be done by the bootloader.
This does show significant degradation in synthetic tests such as
mbw (https://packages.qa.debian.org/m/mbw.html)
mbw -n 100 100|grep AVG (on a test platform)
Without enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13406 MiB: 100.00000 Copy: 745.913 MiB/s
AVG Method: DUMB Elapsed: 0.06746 MiB: 100.00000 Copy: 1482.357 MiB/s
AVG Method: MCBLOCK Elapsed: 0.03058 MiB: 100.00000 Copy: 3270.569 MiB/s
After enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13757 MiB: 100.00000 Copy: 726.913 MiB/s
AVG Method: DUMB Elapsed: 0.12024 MiB: 100.00000 Copy: 831.668 MiB/s
AVG Method: MCBLOCK Elapsed: 0.09243 MiB: 100.00000 Copy: 1081.942 MiB/s
Most benchmarks are designed for specific performance analysis, so
overall usecase must be considered before making a decision to
enable/disable the erratum workaround.
Pending internal investigation, the erratum is kept disabled by default.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Tony Lindgren <tony@atomide.com>
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-08-06 10:54:24 -05:00
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#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
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2013-10-10 13:13:48 +05:30
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2010-06-16 22:19:48 +05:30
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/* Secure PPA(Primary Protected Application) APIs */
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2021-03-14 18:35:44 +02:00
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#define OMAP4_PPA_SERVICE_0 0x21
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2011-01-09 02:59:09 +05:30
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#define OMAP4_PPA_L2_POR_INDEX 0x23
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2010-06-16 22:19:48 +05:30
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#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
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2020-01-02 16:19:43 -05:00
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#define AM43xx_PPA_SVC_PM_SUSPEND 0x71
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#define AM43xx_PPA_SVC_PM_RESUME 0x72
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2013-09-18 21:43:56 +02:00
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/* Secure RX-51 PPA (Primary Protected Application) APIs */
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#define RX51_PPA_HWRNG 29
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#define RX51_PPA_L2_INVAL 40
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#define RX51_PPA_WRITE_ACR 42
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2010-06-16 22:19:48 +05:30
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#ifndef __ASSEMBLER__
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2011-06-06 17:56:49 +05:30
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extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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2020-01-02 16:19:42 -05:00
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extern void omap_smccc_smc(u32 fn, u32 arg);
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extern void omap_smc1(u32 fn, u32 arg);
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2011-06-06 17:56:49 +05:30
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extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
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2013-09-08 09:43:29 +02:00
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extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
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2012-10-02 00:17:06 +05:30
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extern int omap_secure_ram_reserve_memblock(void);
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2017-11-27 08:57:26 -08:00
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extern u32 save_secure_ram_context(u32 args_pa);
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2022-04-28 11:08:16 +02:00
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extern u32 omap3_save_secure_ram(void *save_regs, int size);
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2011-06-06 17:56:49 +05:30
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2013-09-18 21:43:56 +02:00
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extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
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2013-09-20 15:25:07 +02:00
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extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
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2013-09-18 21:43:56 +02:00
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2020-01-02 16:19:41 -05:00
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extern bool optee_available;
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2020-01-02 16:19:40 -05:00
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void omap_secure_init(void);
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2013-11-18 13:56:48 -08:00
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#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
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2013-10-10 13:13:48 +05:30
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void set_cntfreq(void);
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2013-11-18 13:56:48 -08:00
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#else
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static inline void set_cntfreq(void)
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{
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}
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#endif
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2010-06-16 22:19:48 +05:30
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#endif /* __ASSEMBLER__ */
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2011-06-06 17:56:49 +05:30
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#endif /* OMAP_ARCH_OMAP_SECURE_H */
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