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Merge master.kernel.org:/home/rmk/linux-2.6-arm

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* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4872/1: Replaces buggy macro in S3C2410 irq include
  [ARM] 4870/1: fix signal return code when enable CONFIG_OABI_COMPAT
  [ARM] 4869/1: ARM: OMAP: Fix compile for mcbsp
  [ARM] 4865/1: Register the F75375 device in the GLAN Tank platform code
  [ARM] 4864/1: Enable write buffer coalescing on IOP
  [ARM] 4863/1: AT91: CAP9 USART definitions for early debug
  [ARM] 4861/1: AT91: Update maintainer email address (again)
  ARM: OMAP1: Fix typo in OMAP1 MPU clock source initialization
  ARM: OMAP: Fix DMA CLINK mask, clear spurious interrupt
  ARM: OMAP: Fix chain_a_transfer return value
  ARM: OMAP: Fix missing makefile options
  ARM: OMAP: Fix GPIO IRQ unmask
  ARM: OMAP: Fix clockevent support for hrtimers
This commit is contained in:
Linus Torvalds 2008-03-20 09:50:21 -07:00
commit 00c04db982
13 changed files with 55 additions and 15 deletions
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2
MAINTAINERS
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@ -452,7 +452,7 @@ S: Maintained
ARM/ATMEL AT91RM9200 ARM ARCHITECTURE
P: Andrew Victor
M: andrew@sanpeople.com
M: linux@maxim.org.za
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
W: http://maxim.org.za/at91_26.html
S: Maintained

1
arch/arm/Kconfig
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@ -469,6 +469,7 @@ config ARCH_OMAP
bool "TI OMAP"
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
Support for TI's OMAP platform (OMAP1 and OMAP2).

4
arch/arm/kernel/signal.c
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@ -26,8 +26,8 @@
/*
* For ARM syscalls, we encode the syscall number into the instruction.
*/
#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn))
#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn))
#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE))
#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE))
/*
* With EABI, the syscall number has to be loaded into r7.

12
arch/arm/mach-iop32x/glantank.c
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@ -14,8 +14,10 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/f75375s.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
@ -167,11 +169,21 @@ static struct platform_device glantank_serial_device = {
.resource = &glantank_uart_resource,
};
static struct f75375s_platform_data glantank_f75375s = {
.pwm = { 255, 255 },
.pwm_enable = { 0, 0 },
};
static struct i2c_board_info __initdata glantank_i2c_devices[] = {
{
I2C_BOARD_INFO("rtc-rs5c372", 0x32),
.type = "rs5c372a",
},
{
I2C_BOARD_INFO("f75375", 0x2e),
.type = "f75375",
.platform_data = &glantank_f75375s,
},
};
static void glantank_power_off(void)

12
arch/arm/mach-omap1/time.c
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@ -132,13 +132,20 @@ static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
timer->cntl = timerflags;
}
static inline void omap_mpu_timer_stop(int nr)
{
volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
timer->cntl &= ~MPU_TIMER_ST;
}
/*
* ---------------------------------------------------------------------------
* MPU timer 1 ... count down to zero, interrupt, reload
* ---------------------------------------------------------------------------
*/
static int omap_mpu_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
struct clock_event_device *evt)
{
omap_mpu_timer_start(0, cycles, 0);
return 0;
@ -152,6 +159,7 @@ static void omap_mpu_set_mode(enum clock_event_mode mode,
omap_mpu_set_autoreset(0);
break;
case CLOCK_EVT_MODE_ONESHOT:
omap_mpu_timer_stop(0);
omap_mpu_remove_autoreset(0);
break;
case CLOCK_EVT_MODE_UNUSED:
@ -163,7 +171,7 @@ static void omap_mpu_set_mode(enum clock_event_mode mode,
static struct clock_event_device clockevent_mpu_timer1 = {
.name = "mpu_timer1",
.features = CLOCK_EVT_FEAT_PERIODIC, CLOCK_EVT_FEAT_ONESHOT,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_next_event = omap_mpu_set_next_event,
.set_mode = omap_mpu_set_mode,

4
arch/arm/mm/proc-xscale.S
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@ -114,6 +114,10 @@ clean_addr: .word CLEAN_ADDR
* Nothing too exciting at the moment
*/
ENTRY(cpu_xscale_proc_init)
@ enable write buffer coalescing. Some bootloader disable it
mrc p15, 0, r1, c1, c0, 1
bic r1, r1, #1
mcr p15, 0, r1, c1, c0, 1
mov pc, lr
/*

1
arch/arm/plat-omap/Kconfig
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@ -11,7 +11,6 @@ choice
config ARCH_OMAP1
bool "TI OMAP1"
select GENERIC_CLOCKEVENTS
config ARCH_OMAP2
bool "TI OMAP2"

5
arch/arm/plat-omap/Makefile
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@ -14,9 +14,14 @@ obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
# OCPI interconnect support for 1710, 1610 and 5912
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
obj-$(CONFIG_I2C_OMAP) += i2c.o
# OMAP mailbox framework
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o

9
arch/arm/plat-omap/dma.c
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@ -1020,12 +1020,12 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
}
w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
w &= ~(0x0f);
w &= ~(0x1f);
w |= lch_queue;
OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
w &= ~(0x0f);
w &= ~(0x1f);
w |= (dma_chan[lch_queue].next_linked_ch);
OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
}
@ -1248,7 +1248,7 @@ EXPORT_SYMBOL(omap_dma_chain_status);
* @param frame_count
* @param callbk_data - channel callback parameter data.
*
* @return - Success : start_dma status
* @return - Success : 0
* Failure: -EINVAL/-EBUSY
*/
int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
@ -1367,7 +1367,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
}
return start_dma;
return 0;
}
EXPORT_SYMBOL(omap_dma_chain_a_transfer);
@ -1663,6 +1663,7 @@ static int omap2_dma_handle_ch(int ch)
if (!status) {
if (printk_ratelimit())
printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
return 0;
}
if (unlikely(dma_chan[ch].dev_id == -1)) {

3
arch/arm/plat-omap/gpio.c
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@ -1134,10 +1134,9 @@ static void gpio_mask_irq(unsigned int irq)
static void gpio_unmask_irq(unsigned int irq)
{
unsigned int gpio = irq - IH_GPIO_BASE;
unsigned int gpio_idx = get_gpio_index(gpio);
struct gpio_bank *bank = get_irq_chip_data(irq);
_set_gpio_irqenable(bank, gpio_idx, 1);
_set_gpio_irqenable(bank, gpio, 1);
}
static struct irq_chip gpio_irq_chip = {

7
include/asm-arm/arch-at91/at91cap9.h
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@ -97,12 +97,17 @@
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
* Internal Memory.
*/

8
include/asm-arm/arch-omap/dsp_common.h
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@ -24,11 +24,17 @@
#ifndef ASM_ARCH_DSP_COMMON_H
#define ASM_ARCH_DSP_COMMON_H
#ifdef CONFIG_ARCH_OMAP1
#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
extern void omap_dsp_request_mpui(void);
extern void omap_dsp_release_mpui(void);
extern int omap_dsp_request_mem(void);
extern int omap_dsp_release_mem(void);
#else
static inline int omap_dsp_request_mem(void)
{
return 0;
}
#define omap_dsp_release_mem() do {} while (0)
#endif
#endif /* ASM_ARCH_DSP_COMMON_H */

2
include/asm-arm/arch-s3c2410/irqs.h
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@ -85,7 +85,7 @@
#define IRQ_EINT23 S3C2410_IRQ(51)
#define IRQ_EINT(x) S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
#define IRQ_LCD_FIFO S3C2410_IRQ(52)
#define IRQ_LCD_FRAME S3C2410_IRQ(53)