Kernel/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2024-12-29 17:23:36 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next

Browse Source 
* clk-samsung:
  clk: samsung: Introduce Exynos8895 clock driver
  clk: samsung: clk-pll: Add support for pll_{1051x,1052x}
  dt-bindings: clock: samsung: Add Exynos8895 SoC
  clk: samsung: gs101: make all ufs related clocks critical
  clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
  dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
  clk: samsung: Fix out-of-bound access of of_match_node()
  dt-bindings: clock: samsung: remove define with number of clocks for FSD
  clk: samsung: fsd: do not define number of clocks in bindings
  clk: samsung: Fix errors reported by checkpatch
  clk: samsung: Fix block comment style warnings reported by checkpatch

* clk-microchip:
  clk: lan966x: add support for lan969x SoC clock driver
  clk: lan966x: prepare driver for lan969x support
  clk: lan966x: make clk_names const char * const
  dt-bindings: clock: add support for lan969x

* clk-imx:
  clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()
  clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore
  clk: imx: clk-scu: fix clk enable state save and restore
  clk: imx: fracn-gppll: fix pll power up
  clk: imx: fracn-gppll: correct PLL initialization flow
  clk: imx: lpcg-scu: SW workaround for errata (e10858)
  clk: imx: add i.MX91 clk
  dt-bindings: clock: Add i.MX91 clock support
  dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
  clk: imx93: Move IMX93_CLK_END macro to clk driver
  clk: imx95-blk-ctl: Add one clock gate for HSIO block
  dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL

* clk-amlogic:
  clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX
  clk: amlogic: axg-audio: use the auxiliary reset driver
  reset: amlogic: Fix small whitespace issue
  reset: amlogic: add auxiliary reset driver support
  reset: amlogic: split the device core and platform probe
  reset: amlogic: move drivers to a dedicated directory
  reset: amlogic: add reset status support
  reset: amlogic: use reset number instead of register count
  reset: amlogic: add driver parameters
  reset: amlogic: make parameters unsigned
  reset: amlogic: use generic data matching function
  reset: amlogic: convert driver to regmap
  dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
  clk: meson: meson8b: remove spinlock
  clk: meson: mpll: Delete a useless spinlock from the MPLL
  clk: meson: s4: pll: fix frac maximum value for hifi_pll
  clk: meson: c3: pll: fix frac maximum value for hifi_pll
  clk: meson: Support PLL with fixed fractional denominators
  clk: meson: s4: pll: hifi_pll support fractional multiplier

* clk-allwinner:
  clk: sunxi-ng: Use of_property_present() for non-boolean properties
  clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
  clk: sunxi-ng: Constify struct ccu_reset_map
  clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
This commit is contained in:
Stephen Boyd 2024-11-18 20:01:28 -08:00
commit 0cf32b1f37
85 changed files with 4659 additions and 516 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml Normal file
View File

@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
oneOf:
- enum:
- amlogic,meson8-clkc
- amlogic,meson8b-clkc
- items:
- const: amlogic,meson8m2-clkc
- const: amlogic,meson8-clkc
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
items:
- const: xtal
- const: ddr_pll
- const: clk_32k
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#reset-cells'
additionalProperties: false

51
Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
View File

@ -1,51 +0,0 @@
* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
supplies clock to various controllers within the SoC.
Required Properties:
- compatible: must be one of:
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
- #clock-cells: should be 1.
- #reset-cells: should be 1.
- clocks: list of clock phandles, one for each entry in clock-names
- clock-names: should contain the following:
* "xtal": the 24MHz system oscillator
* "ddr_pll": the DDR PLL clock
* "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
Parent node should have the following properties :
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
- reg: base address and size of the HHI system control register space.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
used in device tree sources.
Similarly a preprocessor macro for each reset line is defined in
dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
device tree sources).
Example: Clock controller node:
clkc: clock-controller {
compatible = "amlogic,meson8b-clkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart_AO: serial@c81004c0 {
compatible = "amlogic,meson-uart";
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
};

1
Documentation/devicetree/bindings/clock/imx93-clock.yaml
View File

@ -16,6 +16,7 @@ description: |
properties:
compatible:
enum:
- fsl,imx91-ccm
- fsl,imx93-ccm
reg:

13
Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
View File

@ -16,7 +16,18 @@ description: |
properties:
compatible:
const: microchip,lan966x-gck
oneOf:
- enum:
- microchip,lan966x-gck
- microchip,lan9691-gck
- items:
- enum:
- microchip,lan9698-gck
- microchip,lan9696-gck
- microchip,lan9694-gck
- microchip,lan9693-gck
- microchip,lan9692-gck
- const: microchip,lan9691-gck
reg:
minItems: 1

5
Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
View File

@ -13,9 +13,10 @@ properties:
compatible:
items:
- enum:
- nxp,imx95-lvds-csr
- nxp,imx95-display-csr
- nxp,imx95-camera-csr
- nxp,imx95-display-csr
- nxp,imx95-hsio-blk-ctl
- nxp,imx95-lvds-csr
- nxp,imx95-netcmix-blk-ctrl
- nxp,imx95-vpu-csr
- const: syscon

239
Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml Normal file
View File

@ -0,0 +1,239 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos8895 SoC clock controller
maintainers:
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Exynos8895 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. The root clock in that root tree
is an external clock: OSCCLK (26 MHz). This external clock must be defined
as a fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynos8895.h' header.
properties:
compatible:
enum:
- samsung,exynos8895-cmu-fsys0
- samsung,exynos8895-cmu-fsys1
- samsung,exynos8895-cmu-peric0
- samsung,exynos8895-cmu-peric1
- samsung,exynos8895-cmu-peris
- samsung,exynos8895-cmu-top
clocks:
minItems: 1
maxItems: 16
clock-names:
minItems: 1
maxItems: 16
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- "#clock-cells"
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos8895-cmu-fsys0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS0 BUS clock (from CMU_TOP)
- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: dpgtc
- const: mmc
- const: ufs
- const: usbdrd30
- if:
properties:
compatible:
contains:
const: samsung,exynos8895-cmu-fsys1
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS1 BUS clock (from CMU_TOP)
- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: pcie
- const: ufs
- const: mmc
- if:
properties:
compatible:
contains:
const: samsung,exynos8895-cmu-peric0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIC0 BUS clock (from CMU_TOP)
- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: uart
- const: usi0
- const: usi1
- const: usi2
- const: usi3
- if:
properties:
compatible:
contains:
const: samsung,exynos8895-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIC1 BUS clock (from CMU_TOP)
- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: speedy
- const: cam0
- const: cam1
- const: uart
- const: usi4
- const: usi5
- const: usi6
- const: usi7
- const: usi8
- const: usi9
- const: usi10
- const: usi11
- const: usi12
- const: usi13
- if:
properties:
compatible:
contains:
const: samsung,exynos8895-cmu-peris
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIS BUS clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- if:
properties:
compatible:
contains:
const: samsung,exynos8895-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/samsung,exynos8895.h>
cmu_fsys1: clock-controller@11400000 {
compatible = "samsung,exynos8895-cmu-fsys1";
reg = <0x11400000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
};
...

78
drivers/clk/clk-lan966x.c
View File

@ -24,13 +24,20 @@
#define DIV_MAX 255
static const char *clk_names[N_CLOCKS] = {
static const char * const lan966x_clk_names[] = {
"qspi0", "qspi1", "qspi2", "sdmmc0",
"pi", "mcan0", "mcan1", "flexcom0",
"flexcom1", "flexcom2", "flexcom3",
"flexcom4", "timer1", "usb_refclk",
};
static const char * const lan969x_clk_names[] = {
"qspi0", "qspi2", "sdmmc0", "sdmmc1",
"mcan0", "mcan1", "flexcom0",
"flexcom1", "flexcom2", "flexcom3",
"timer1", "usb_refclk",
};
struct lan966x_gck {
struct clk_hw hw;
void __iomem *reg;
@ -53,7 +60,7 @@ struct clk_gate_soc_desc {
int bit_idx;
};
static const struct clk_gate_soc_desc clk_gate_desc[] = {
static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = {
{ "uhphs", 11 },
{ "udphs", 10 },
{ "mcramc", 9 },
@ -61,6 +68,37 @@ static const struct clk_gate_soc_desc clk_gate_desc[] = {
{ }
};
static const struct clk_gate_soc_desc lan969x_clk_gate_desc[] = {
{ "usb_drd", 10 },
{ "mcramc", 9 },
{ "hmatrix", 8 },
{ }
};
struct lan966x_match_data {
char *name;
const char * const *clk_name;
const struct clk_gate_soc_desc *clk_gate_desc;
u8 num_generic_clks;
u8 num_total_clks;
};
static struct lan966x_match_data lan966x_desc = {
.name = "lan966x",
.clk_name = lan966x_clk_names,
.clk_gate_desc = lan966x_clk_gate_desc,
.num_total_clks = 18,
.num_generic_clks = 14,
};
static struct lan966x_match_data lan969x_desc = {
.name = "lan969x",
.clk_name = lan969x_clk_names,
.clk_gate_desc = lan969x_clk_gate_desc,
.num_total_clks = 15,
.num_generic_clks = 12,
};
static DEFINE_SPINLOCK(clk_gate_lock);
static void __iomem *base;
@ -186,24 +224,26 @@ static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i)
};
static int lan966x_gate_clk_register(struct device *dev,
const struct lan966x_match_data *data,
struct clk_hw_onecell_data *hw_data,
void __iomem *gate_base)
{
int i;
for (int i = data->num_generic_clks; i < data->num_total_clks; ++i) {
int idx = i - data->num_generic_clks;
const struct clk_gate_soc_desc *desc;
for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) {
int idx = i - GCK_GATE_UHPHS;
desc = &data->clk_gate_desc[idx];
hw_data->hws[i] =
devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name,
"lan966x", 0, gate_base,
clk_gate_desc[idx].bit_idx,
devm_clk_hw_register_gate(dev, desc->name,
data->name, 0, gate_base,
desc->bit_idx,
0, &clk_gate_lock);
if (IS_ERR(hw_data->hws[i]))
return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),
"failed to register %s clock\n",
clk_gate_desc[idx].name);
desc->name);
}
return 0;
@ -211,13 +251,18 @@ static int lan966x_gate_clk_register(struct device *dev,
static int lan966x_clk_probe(struct platform_device *pdev)
{
const struct lan966x_match_data *data;
struct clk_hw_onecell_data *hw_data;
struct device *dev = &pdev->dev;
void __iomem *gate_base;
struct resource *res;
int i, ret;
hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS),
data = device_get_match_data(dev);
if (!data)
return -EINVAL;
hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, data->num_total_clks),
GFP_KERNEL);
if (!hw_data)
return -ENOMEM;
@ -228,10 +273,10 @@ static int lan966x_clk_probe(struct platform_device *pdev)
init.ops = &lan966x_gck_ops;
hw_data->num = GCK_GATE_UHPHS;
hw_data->num = data->num_generic_clks;
for (i = 0; i < GCK_GATE_UHPHS; i++) {
init.name = clk_names[i];
for (i = 0; i < data->num_generic_clks; i++) {
init.name = data->clk_name[i];
hw_data->hws[i] = lan966x_gck_clk_register(dev, i);
if (IS_ERR(hw_data->hws[i])) {
dev_err(dev, "failed to register %s clock\n",
@ -246,9 +291,9 @@ static int lan966x_clk_probe(struct platform_device *pdev)
if (IS_ERR(gate_base))
return PTR_ERR(gate_base);
hw_data->num = N_CLOCKS;
hw_data->num = data->num_total_clks;
ret = lan966x_gate_clk_register(dev, hw_data, gate_base);
ret = lan966x_gate_clk_register(dev, data, hw_data, gate_base);
if (ret)
return ret;
}
@ -257,7 +302,8 @@ static int lan966x_clk_probe(struct platform_device *pdev)
}
static const struct of_device_id lan966x_clk_dt_ids[] = {
{ .compatible = "microchip,lan966x-gck", },
{ .compatible = "microchip,lan966x-gck", .data = &lan966x_desc },
{ .compatible = "microchip,lan9691-gck", .data = &lan969x_desc },
{ }
};
MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);

10
drivers/clk/imx/clk-fracn-gppll.c
View File

@ -254,9 +254,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
FIELD_PREP(PLL_MFI_MASK, rate->mfi);
writel_relaxed(pll_div, pll->base + PLL_DIV);
readl(pll->base + PLL_DIV);
if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
readl(pll->base + PLL_NUMERATOR);
}
/* Wait for 5us according to fracn mode pll doc */
@ -265,6 +267,7 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
/* Enable Powerup */
tmp |= POWERUP_MASK;
writel_relaxed(tmp, pll->base + PLL_CTRL);
readl(pll->base + PLL_CTRL);
/* Wait Lock */
ret = clk_fracn_gppll_wait_lock(pll);
@ -302,14 +305,15 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw)
val |= POWERUP_MASK;
writel_relaxed(val, pll->base + PLL_CTRL);
val |= CLKMUX_EN;
writel_relaxed(val, pll->base + PLL_CTRL);
readl(pll->base + PLL_CTRL);
ret = clk_fracn_gppll_wait_lock(pll);
if (ret)
return ret;
val |= CLKMUX_EN;
writel_relaxed(val, pll->base + PLL_CTRL);
val &= ~CLKMUX_BYPASS;
writel_relaxed(val, pll->base + PLL_CTRL);

4
drivers/clk/imx/clk-imx8-acm.c
View File

@ -294,9 +294,9 @@ static int clk_imx_acm_attach_pm_domains(struct device *dev,
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
if (IS_ERR(dev_pm->pd_dev_link[i])) {
if (!dev_pm->pd_dev_link[i]) {
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
ret = PTR_ERR(dev_pm->pd_dev_link[i]);
ret = -EINVAL;
goto detach_pm;
}
}

63
drivers/clk/imx/clk-imx93.c
View File

@ -15,6 +15,11 @@
#include "clk.h"
#define IMX93_CLK_END 207
#define PLAT_IMX93 BIT(0)
#define PLAT_IMX91 BIT(1)
enum clk_sel {
LOW_SPEED_IO_SEL,
NON_IO_SEL,
@ -53,6 +58,7 @@ static const struct imx93_clk_root {
u32 off;
enum clk_sel sel;
unsigned long flags;
unsigned long plat;
} root_array[] = {
/* a55/m33/bus critical clk for system run */
{ IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
@ -63,7 +69,7 @@ static const struct imx93_clk_root {
{ IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
{ IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
{ IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, },
@ -120,15 +126,15 @@ static const struct imx93_clk_root {
{ IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
{ IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, },
{ IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, },
{ IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, },
{ IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, },
{ IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, },
{ IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, },
{ IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, },
{ IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, },
{ IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, },
{ IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, },
@ -137,13 +143,16 @@ static const struct imx93_clk_root {
{ IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, },
{ IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, },
{ IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, },
{ IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, },
{ IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, },
{ IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX91_CLK_ENET1_QOS_TSN, "enet1_qos_tsn_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX91, },
{ IMX91_CLK_ENET_TIMER, "enet_timer_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX91, },
{ IMX91_CLK_ENET2_REGULAR, "enet2_regular_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX91, },
{ IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, }
};
@ -155,6 +164,7 @@ static const struct imx93_clk_ccgr {
u32 off;
unsigned long flags;
u32 *shared_count;
unsigned long plat;
} ccgr_array[] = {
{ IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, },
/* M33 critical clk for system run */
@ -244,8 +254,10 @@ static const struct imx93_clk_ccgr {
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
{ IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, },
{ IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, },
{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, },
{ IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX93, },
{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX93, },
{ IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, },
{ IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, },
/* Critical because clk accessed during CPU idle */
{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL},
{ IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },
@ -265,6 +277,7 @@ static int imx93_clocks_probe(struct platform_device *pdev)
const struct imx93_clk_ccgr *ccgr;
void __iomem *base, *anatop_base;
int i, ret;
const unsigned long plat = (unsigned long)device_get_match_data(&pdev->dev);
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
IMX93_CLK_END), GFP_KERNEL);
@ -314,17 +327,20 @@ static int imx93_clocks_probe(struct platform_device *pdev)
for (i = 0; i < ARRAY_SIZE(root_array); i++) {
root = &root_array[i];
clks[root->clk] = imx93_clk_composite_flags(root->name,
parent_names[root->sel],
4, base + root->off, 3,
root->flags);
if (!root->plat || root->plat & plat)
clks[root->clk] = imx93_clk_composite_flags(root->name,
parent_names[root->sel],
4, base + root->off, 3,
root->flags);
}
for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) {
ccgr = &ccgr_array[i];
clks[ccgr->clk] = imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name,
ccgr->flags, base + ccgr->off, 0, 1, 1, 3,
ccgr->shared_count);
if (!ccgr->plat || ccgr->plat & plat)
clks[ccgr->clk] = imx93_clk_gate(NULL,
ccgr->name, ccgr->parent_name,
ccgr->flags, base + ccgr->off, 0, 1, 1, 3,
ccgr->shared_count);
}
clks[IMX93_CLK_A55_SEL] = imx_clk_hw_mux2("a55_sel", base + 0x4820, 0, 1, a55_core_sels,
@ -354,7 +370,8 @@ static int imx93_clocks_probe(struct platform_device *pdev)
}
static const struct of_device_id imx93_clk_of_match[] = {
{ .compatible = "fsl,imx93-ccm" },
{ .compatible = "fsl,imx93-ccm", .data = (void *)PLAT_IMX93 },
{ .compatible = "fsl,imx91-ccm", .data = (void *)PLAT_IMX91 },
{ /* Sentinel */ },
};
MODULE_DEVICE_TABLE(of, imx93_clk_of_match);

20
drivers/clk/imx/clk-imx95-blk-ctl.c
View File

@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
.clk_reg_offset = 0,
};
static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
[0] = {
.name = "hsio_blk_ctl_clk",
.parent_names = (const char *[]){ "hsio_pll", },
.num_parents = 1,
.reg = 0,
.bit_idx = 6,
.bit_width = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
.num_clks = 1,
.clk_dev_data = hsio_blk_ctl_clk_dev_data,
.clk_reg_offset = 0,
};
static int imx95_bc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
{ .compatible = "nxp,imx95-display-master-csr", },
{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
{ /* Sentinel */ },

41
drivers/clk/imx/clk-lpcg-scu.c
View File

@ -6,10 +6,12 @@
#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/units.h>
#include "clk-scu.h"
@ -41,6 +43,29 @@ struct clk_lpcg_scu {
#define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
/* e10858 -LPCG clock gating register synchronization errata */
static void lpcg_e10858_writel(unsigned long rate, void __iomem *reg, u32 val)
{
writel(val, reg);
if (rate >= 24 * HZ_PER_MHZ || rate == 0) {
/*
* The time taken to access the LPCG registers from the AP core
* through the interconnect is longer than the minimum delay
* of 4 clock cycles required by the errata.
* Adding a readl will provide sufficient delay to prevent
* back-to-back writes.
*/
readl(reg);
} else {
/*
* For clocks running below 24MHz, wait a minimum of
* 4 clock cycles.
*/
ndelay(4 * (DIV_ROUND_UP(1000 * HZ_PER_MHZ, rate)));
}
}
static int clk_lpcg_scu_enable(struct clk_hw *hw)
{
struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
@ -57,7 +82,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw)
val |= CLK_GATE_SCU_LPCG_HW_SEL;
reg |= val << clk->bit_idx;
writel(reg, clk->reg);
lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg);
spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
@ -74,7 +100,7 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw)
reg = readl_relaxed(clk->reg);
reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
writel(reg, clk->reg);
lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg);
spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
}
@ -135,6 +161,9 @@ static int __maybe_unused imx_clk_lpcg_scu_suspend(struct device *dev)
{
struct clk_lpcg_scu *clk = dev_get_drvdata(dev);
if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg")))
return 0;
clk->state = readl_relaxed(clk->reg);
dev_dbg(dev, "save lpcg state 0x%x\n", clk->state);
@ -145,13 +174,11 @@ static int __maybe_unused imx_clk_lpcg_scu_resume(struct device *dev)
{
struct clk_lpcg_scu *clk = dev_get_drvdata(dev);
/*
* FIXME: Sometimes writes don't work unless the CPU issues
* them twice
*/
if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg")))
return 0;
writel(clk->state, clk->reg);
writel(clk->state, clk->reg);
lpcg_e10858_writel(0, clk->reg, clk->state);
dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state);
return 0;

2
drivers/clk/imx/clk-scu.c
View File

@ -596,7 +596,7 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
else
clk->rate = clk_hw_get_rate(&clk->hw);
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
clk->is_enabled = clk_hw_is_prepared(&clk->hw);
if (clk->parent)
dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),

1
drivers/clk/meson/Kconfig
View File

@ -106,6 +106,7 @@ config COMMON_CLK_AXG_AUDIO
select COMMON_CLK_MESON_SCLK_DIV
select COMMON_CLK_MESON_CLKC_UTILS
select REGMAP_MMIO
depends on RESET_MESON_AUX
help
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.

109
drivers/clk/meson/axg-audio.c
View File

@ -15,6 +15,8 @@
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <soc/amlogic/reset-meson-aux.h>
#include "meson-clkc-utils.h"
#include "axg-audio.h"
#include "clk-regmap.h"
@ -1678,84 +1680,6 @@ static struct clk_regmap *const sm1_clk_regmaps[] = {
&sm1_earcrx_dmac_clk,
};
struct axg_audio_reset_data {
struct reset_controller_dev rstc;
struct regmap *map;
unsigned int offset;
};
static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
unsigned long id,
unsigned int *reg,
unsigned int *bit)
{
unsigned int stride = regmap_get_reg_stride(rst->map);
*reg = (id / (stride * BITS_PER_BYTE)) * stride;
*reg += rst->offset;
*bit = id % (stride * BITS_PER_BYTE);
}
static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct axg_audio_reset_data *rst =
container_of(rcdev, struct axg_audio_reset_data, rstc);
unsigned int offset, bit;
axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
regmap_update_bits(rst->map, offset, BIT(bit),
assert ? BIT(bit) : 0);
return 0;
}
static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct axg_audio_reset_data *rst =
container_of(rcdev, struct axg_audio_reset_data, rstc);
unsigned int val, offset, bit;
axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
regmap_read(rst->map, offset, &val);
return !!(val & BIT(bit));
}
static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return axg_audio_reset_update(rcdev, id, true);
}
static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return axg_audio_reset_update(rcdev, id, false);
}
static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = axg_audio_reset_assert(rcdev, id);
if (ret)
return ret;
return axg_audio_reset_deassert(rcdev, id);
}
static const struct reset_control_ops axg_audio_rstc_ops = {
.assert = axg_audio_reset_assert,
.deassert = axg_audio_reset_deassert,
.reset = axg_audio_reset_toggle,
.status = axg_audio_reset_status,
};
static struct regmap_config axg_audio_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
@ -1766,16 +1690,14 @@ struct audioclk_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
struct meson_clk_hw_data hw_clks;
unsigned int reset_offset;
unsigned int reset_num;
unsigned int max_register;
const char *rst_drvname;
};
static int axg_audio_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct audioclk_data *data;
struct axg_audio_reset_data *rst;
struct regmap *map;
void __iomem *regs;
struct clk_hw *hw;
@ -1834,22 +1756,11 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
if (ret)
return ret;
/* Stop here if there is no reset */
if (!data->reset_num)
return 0;
/* Register auxiliary reset driver when applicable */
if (data->rst_drvname)
ret = devm_meson_rst_aux_register(dev, map, data->rst_drvname);
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
rst->map = map;
rst->offset = data->reset_offset;
rst->rstc.nr_resets = data->reset_num;
rst->rstc.ops = &axg_audio_rstc_ops;
rst->rstc.of_node = dev->of_node;
rst->rstc.owner = THIS_MODULE;
return devm_reset_controller_register(dev, &rst->rstc);
return ret;
}
static const struct audioclk_data axg_audioclk_data = {
@ -1869,9 +1780,8 @@ static const struct audioclk_data g12a_audioclk_data = {
.hws = g12a_audio_hw_clks,
.num = ARRAY_SIZE(g12a_audio_hw_clks),
},
.reset_offset = AUDIO_SW_RESET,
.reset_num = 26,
.max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
.rst_drvname = "rst-g12a",
};
static const struct audioclk_data sm1_audioclk_data = {
@ -1881,9 +1791,8 @@ static const struct audioclk_data sm1_audioclk_data = {
.hws = sm1_audio_hw_clks,
.num = ARRAY_SIZE(sm1_audio_hw_clks),
},
.reset_offset = AUDIO_SM1_SW_RESET0,
.reset_num = 39,
.max_register = AUDIO_EARCRX_DMAC_CLK_CTRL,
.rst_drvname = "rst-sm1",
};
static const struct of_device_id clkc_match_table[] = {

6
drivers/clk/meson/axg.c
View File

@ -23,8 +23,6 @@
#include <dt-bindings/clock/axg-clkc.h>
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap axg_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@ -506,7 +504,6 @@ static struct clk_regmap axg_mpll0_div = {
.shift = 0,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
@ -557,7 +554,6 @@ static struct clk_regmap axg_mpll1_div = {
.shift = 1,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
@ -613,7 +609,6 @@ static struct clk_regmap axg_mpll2_div = {
.shift = 2,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
@ -664,7 +659,6 @@ static struct clk_regmap axg_mpll3_div = {
.shift = 3,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){

1
drivers/clk/meson/c3-pll.c
View File

@ -361,6 +361,7 @@ static struct clk_regmap hifi_pll_dco = {
.range = &c3_gp0_pll_mult_range,
.init_regs = c3_hifi_init_regs,
.init_count = ARRAY_SIZE(c3_hifi_init_regs),
.frac_max = 100000,
},
.hw.init = &(struct clk_init_data) {
.name = "hifi_pll_dco",

11
drivers/clk/meson/clk-mpll.c
View File

@ -112,26 +112,15 @@ static int mpll_set_rate(struct clk_hw *hw,
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
unsigned int sdm, n2;
unsigned long flags = 0;
params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
if (mpll->lock)
spin_lock_irqsave(mpll->lock, flags);
else
__acquire(mpll->lock);
/* Set the fractional part */
meson_parm_write(clk->map, &mpll->sdm, sdm);
/* Set the integer divider part */
meson_parm_write(clk->map, &mpll->n2, n2);
if (mpll->lock)
spin_unlock_irqrestore(mpll->lock, flags);
else
__release(mpll->lock);
return 0;
}

1
drivers/clk/meson/clk-mpll.h
View File

@ -20,7 +20,6 @@ struct meson_clk_mpll_data {
struct parm misc;
const struct reg_sequence *init_regs;
unsigned int init_count;
spinlock_t *lock;
u8 flags;
};

8
drivers/clk/meson/clk-pll.c
View File

@ -57,12 +57,13 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate,
struct meson_clk_pll_data *pll)
{
u64 rate = (u64)parent_rate * m;
unsigned int frac_max = pll->frac_max ? pll->frac_max :
(1 << pll->frac.width);
if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
u64 frac_rate = (u64)parent_rate * frac;
rate += DIV_ROUND_UP_ULL(frac_rate,
(1 << pll->frac.width));
rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
}
return DIV_ROUND_UP_ULL(rate, n);
@ -100,7 +101,8 @@ static unsigned int __pll_params_with_frac(unsigned long rate,
unsigned int n,
struct meson_clk_pll_data *pll)
{
unsigned int frac_max = (1 << pll->frac.width);
unsigned int frac_max = pll->frac_max ? pll->frac_max :
(1 << pll->frac.width);
u64 val = (u64)rate * n;
/* Bail out if we are already over the requested rate */

1
drivers/clk/meson/clk-pll.h
View File

@ -43,6 +43,7 @@ struct meson_clk_pll_data {
unsigned int init_count;
const struct pll_params_table *table;
const struct pll_mult_range *range;
unsigned int frac_max;
u8 flags;
};

6
drivers/clk/meson/g12a.c
View File

@ -28,8 +28,6 @@
#include <dt-bindings/clock/g12a-clkc.h>
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap g12a_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@ -2225,7 +2223,6 @@ static struct clk_regmap g12a_mpll0_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll0_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
},
@ -2279,7 +2276,6 @@ static struct clk_regmap g12a_mpll1_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll1_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
},
@ -2333,7 +2329,6 @@ static struct clk_regmap g12a_mpll2_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll2_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
},
@ -2387,7 +2382,6 @@ static struct clk_regmap g12a_mpll3_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll3_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
},

6
drivers/clk/meson/gxbb.c
View File

@ -19,8 +19,6 @@
#include <dt-bindings/clock/gxbb-clkc.h>
static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
PLL_PARAMS(32, 1),
PLL_PARAMS(33, 1),
@ -731,7 +729,6 @@ static struct clk_regmap gxbb_mpll0_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
@ -760,7 +757,6 @@ static struct clk_regmap gxl_mpll0_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
@ -812,7 +808,6 @@ static struct clk_regmap gxbb_mpll1_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
@ -855,7 +850,6 @@ static struct clk_regmap gxbb_mpll2_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",

10
drivers/clk/meson/meson8b.c
View File

@ -25,8 +25,6 @@
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
static DEFINE_SPINLOCK(meson_clk_lock);
struct meson8b_clk_reset {
struct reset_controller_dev reset;
struct regmap *regmap;
@ -492,7 +490,6 @@ static struct clk_regmap meson8b_mpll0_div = {
.shift = 25,
.width = 1,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
@ -537,7 +534,6 @@ static struct clk_regmap meson8b_mpll1_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
@ -582,7 +578,6 @@ static struct clk_regmap meson8b_mpll2_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
@ -3702,7 +3697,6 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
container_of(rcdev, struct meson8b_clk_reset, reset);
const struct meson8b_clk_reset_line *reset;
unsigned int value = 0;
unsigned long flags;
if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
return -EINVAL;
@ -3712,13 +3706,9 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
if (assert != reset->active_low)
value = BIT(reset->bit_idx);
spin_lock_irqsave(&meson_clk_lock, flags);
regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
BIT(reset->bit_idx), value);
spin_unlock_irqrestore(&meson_clk_lock, flags);
return 0;
}

13
drivers/clk/meson/s4-pll.c
View File

@ -17,8 +17,6 @@
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
static DEFINE_SPINLOCK(meson_clk_lock);
/*
* These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
* The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable
@ -329,7 +327,6 @@ static struct clk_regmap s4_gp0_pll = {
* Internal hifi pll emulation configuration parameters
*/
static const struct reg_sequence s4_hifi_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
@ -354,6 +351,11 @@ static struct clk_regmap s4_hifi_pll_dco = {
.shift = 10,
.width = 5,
},
.frac = {
.reg_off = ANACTRL_HIFIPLL_CTRL1,
.shift = 0,
.width = 17,
},
.l = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
.shift = 31,
@ -367,6 +369,7 @@ static struct clk_regmap s4_hifi_pll_dco = {
.range = &s4_gp0_pll_mult_range,
.init_regs = s4_hifi_init_regs,
.init_count = ARRAY_SIZE(s4_hifi_init_regs),
.frac_max = 100000,
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
@ -542,7 +545,6 @@ static struct clk_regmap s4_mpll0_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll0_init_regs,
.init_count = ARRAY_SIZE(s4_mpll0_init_regs),
},
@ -596,7 +598,6 @@ static struct clk_regmap s4_mpll1_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll1_init_regs,
.init_count = ARRAY_SIZE(s4_mpll1_init_regs),
},
@ -650,7 +651,6 @@ static struct clk_regmap s4_mpll2_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll2_init_regs,
.init_count = ARRAY_SIZE(s4_mpll2_init_regs),
},
@ -704,7 +704,6 @@ static struct clk_regmap s4_mpll3_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll3_init_regs,
.init_count = ARRAY_SIZE(s4_mpll3_init_regs),
},

1
drivers/clk/samsung/Makefile
View File

@ -20,6 +20,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o

2
drivers/clk/samsung/clk-exynos-audss.c
View File

@ -4,7 +4,7 @@
* Author: Padmavathi Venna <padma.v@samsung.com>
*
* Common Clock Framework support for Audio Subsystem Clock Controller.
*/
*/
#include <linux/slab.h>
#include <linux/io.h>

2
drivers/clk/samsung/clk-exynos3250.c
View File

@ -260,7 +260,7 @@ static const struct samsung_mux_clock mux_clks[] __initconst = {
/* SRC_TOP0 */
MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p, SRC_TOP0, 24, 1),
MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),

2
drivers/clk/samsung/clk-exynos4.c
View File

@ -5,7 +5,7 @@
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* Common Clock Framework support for all Exynos4 SoCs.
*/
*/
#include <dt-bindings/clock/exynos4.h>
#include <linux/slab.h>

2
drivers/clk/samsung/clk-exynos4412-isp.c
View File

@ -4,7 +4,7 @@
* Author: Marek Szyprowski <m.szyprowski@samsung.com>
*
* Common Clock Framework support for Exynos4412 ISP module.
*/
*/
#include <dt-bindings/clock/exynos4.h>
#include <linux/slab.h>

2
drivers/clk/samsung/clk-exynos5250.c
View File

@ -5,7 +5,7 @@
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* Common Clock Framework support for Exynos5250 SoC.
*/
*/
#include <dt-bindings/clock/exynos5250.h>
#include <linux/clk-provider.h>

4
drivers/clk/samsung/clk-exynos5260.c
View File

@ -1458,7 +1458,7 @@ static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
NULL, 0, 125000000),
FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
"phyclk_mipi_dphy_4l_m_txbyte_clkhs", NULL,
0, 187500000),
FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
NULL, 0, 24000000),
@ -1629,7 +1629,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
mout_isp1_media_400_p,
MUX_SEL_TOP_ISP10, 4, 1),
MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
MUX_SEL_TOP_ISP10, 8 , 1),
MUX_SEL_TOP_ISP10, 8, 1),
MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
mout_isp1_media_266_p,
MUX_SEL_TOP_ISP10, 16, 1),

2
drivers/clk/samsung/clk-exynos5410.c
View File

@ -4,7 +4,7 @@
* Author: Tarek Dakhran <t.dakhran@samsung.com>
*
* Common Clock Framework support for Exynos5410 SoC.
*/
*/
#include <dt-bindings/clock/exynos5410.h>

6
drivers/clk/samsung/clk-exynos5420.c
View File

@ -5,7 +5,7 @@
* Chander Kashyap <k.chander@samsung.com>
*
* Common Clock Framework support for Exynos5420 SoC.
*/
*/
#include <dt-bindings/clock/exynos5420.h>
#include <linux/slab.h>
@ -295,8 +295,8 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
/* list of all parent clocks */
PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll"};
PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
PNAME(mout_cpu_p) = {"mout_apll", "mout_mspll_cpu"};
PNAME(mout_kfc_p) = {"mout_kpll", "mout_mspll_kfc"};
PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};

2
drivers/clk/samsung/clk-exynos7.c
View File

@ -2,7 +2,7 @@
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
*/
*/
#include <linux/clk-provider.h>
#include <linux/of.h>

2803
drivers/clk/samsung/clk-exynos8895.c Normal file
View File

File diff suppressed because it is too large Load Diff

290
drivers/clk/samsung/clk-exynosautov920.c
View File

@ -19,6 +19,10 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
/* ---- CMU_TOP ------------------------------------------------------------ */
@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon
"mout_shared5_pll", 1, 3, 0),
FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
"mout_shared5_pll", 1, 4, 0),
FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
"oscclk", 1, 2, 0),
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.clk_name = "noc",
};
/* ---- CMU_PERIC1 --------------------------------------------------------- */
/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
static const unsigned long peric1_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
};
/* List of parent clocks for Muxes in CMU_PERIC1 */
PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
/* USI09 ~ USI17 */
MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
/* USI_I2C */
MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
/* USI_I3C */
MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
};
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
/* USI09 ~ USI17 */
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
"mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
"mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
"mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
"mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
"mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
"mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
"mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
"mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
"mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
0, 4),
/* USI_I2C */
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
"mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
/* USI_I3C */
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
"mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
};
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.mux_clks = peric1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
.div_clks = peric1_div_clks,
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
.nr_clk_ids = CLKS_NR_PERIC1,
.clk_regs = peric1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
.clk_name = "noc",
};
/* ---- CMU_MISC --------------------------------------------------------- */
/* Register Offset definitions for CMU_MISC (0x10020000) */
#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
#define CLK_CON_DIV_CLKCMU_OTP 0x1800
#define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
static const unsigned long misc_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
CLK_CON_MUX_MUX_CLK_MISC_GIC,
CLK_CON_DIV_CLKCMU_OTP,
CLK_CON_DIV_DIV_CLK_MISC_NOCP,
CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
};
/* List of parent clocks for Muxes in CMU_MISC */
PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
};
static const struct samsung_div_clock misc_div_clks[] __initconst = {
DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
"mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
0, 3),
};
static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
"oscclk", 1, 10, 0),
FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
"oscclk", 1, 2, 0),
};
static const struct samsung_cmu_info misc_cmu_info __initconst = {
.mux_clks = misc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
.div_clks = misc_div_clks,
.nr_div_clks = ARRAY_SIZE(misc_div_clks),
.fixed_factor_clks = misc_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
.nr_clk_ids = CLKS_NR_MISC,
.clk_regs = misc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
.clk_name = "noc",
};
/* ---- CMU_HSI0 --------------------------------------------------------- */
/* Register Offset definitions for CMU_HSI0 (0x16000000) */
#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
static const unsigned long hsi0_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
};
/* List of parent clocks for Muxes in CMU_HSI0 */
PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
};
static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
"mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
0, 4),
};
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
.mux_clks = hsi0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
.div_clks = hsi0_div_clks,
.nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
.nr_clk_ids = CLKS_NR_HSI0,
.clk_regs = hsi0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
.clk_name = "noc",
};
/* ---- CMU_HSI1 --------------------------------------------------------- */
/* Register Offset definitions for CMU_HSI1 (0x16400000) */
#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
static const unsigned long hsi1_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
};
/* List of parent clocks for Muxes in CMU_HSI1 */
PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
};
static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
.mux_clks = hsi1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
.nr_clk_ids = CLKS_NR_HSI1,
.clk_regs = hsi1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
.clk_name = "noc",
};
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
@ -1154,7 +1431,20 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
{
.compatible = "samsung,exynosautov920-cmu-peric0",
.data = &peric0_cmu_info,
}, {
.compatible = "samsung,exynosautov920-cmu-peric1",
.data = &peric1_cmu_info,
}, {
.compatible = "samsung,exynosautov920-cmu-misc",
.data = &misc_cmu_info,
}, {
.compatible = "samsung,exynosautov920-cmu-hsi0",
.data = &hsi0_cmu_info,
}, {
.compatible = "samsung,exynosautov920-cmu-hsi1",
.data = &hsi1_cmu_info,
},
{ }
};
static struct platform_driver exynosautov920_cmu_driver __refdata = {

23
drivers/clk/samsung/clk-fsd.c
View File

@ -82,6 +82,15 @@
#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_CMU (GAT_CMU_FSYS0_SHARED0DIV4 + 1)
#define CLKS_NR_PERIC (PERIC_DOUT_RGMII_CLK + 1)
#define CLKS_NR_FSYS0 (FSYS0_DOUT_FSYS0_PERIBUS_GRP + 1)
#define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)
#define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)
#define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1)
#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)
static const unsigned long cmu_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED0,
PLL_LOCKTIME_PLL_SHARED1,
@ -300,7 +309,7 @@ static const struct samsung_cmu_info cmu_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(cmu_div_clks),
.gate_clks = cmu_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
.nr_clk_ids = CMU_NR_CLK,
.nr_clk_ids = CLKS_NR_CMU,
.clk_regs = cmu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
};
@ -665,7 +674,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
.fixed_clks = peric_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
.nr_clk_ids = PERIC_NR_CLK,
.nr_clk_ids = CLKS_NR_PERIC,
.clk_regs = peric_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
.clk_name = "dout_cmu_pll_shared0_div4",
@ -964,7 +973,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
.fixed_clks = fsys0_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks),
.nr_clk_ids = FSYS0_NR_CLK,
.nr_clk_ids = CLKS_NR_FSYS0,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
.clk_name = "dout_cmu_fsys0_shared1div4",
@ -1136,7 +1145,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
.fixed_clks = fsys1_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks),
.nr_clk_ids = FSYS1_NR_CLK,
.nr_clk_ids = CLKS_NR_FSYS1,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
.clk_name = "dout_cmu_fsys1_shared0div4",
@ -1413,7 +1422,7 @@ static const struct samsung_cmu_info imem_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(imem_div_clks),
.gate_clks = imem_gate_clks,
.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
.nr_clk_ids = IMEM_NR_CLK,
.nr_clk_ids = CLKS_NR_IMEM,
.clk_regs = imem_clk_regs,
.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
};
@ -1538,7 +1547,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = MFC_NR_CLK,
.nr_clk_ids = CLKS_NR_MFC,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
@ -1742,7 +1751,7 @@ static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
.gate_clks = cam_csi_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
.nr_clk_ids = CAM_CSI_NR_CLK,
.nr_clk_ids = CLKS_NR_CAM_CSI,
.clk_regs = cam_csi_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
};

10
drivers/clk/samsung/clk-gs101.c
View File

@ -2775,11 +2775,11 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
"gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
21, 0, 0),
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
"gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
"gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
@ -2806,7 +2806,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
"gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
21, 0, 0),
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
"gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
@ -2842,7 +2842,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
"gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
21, 0, 0),
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
"gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
@ -2850,7 +2850,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
"gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
21, 0, 0),
21, CLK_IS_CRITICAL, 0),
/* TODO: should have a driver for this */
GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
"gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",

2
drivers/clk/samsung/clk-pll.c
View File

@ -1370,6 +1370,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
break;
case pll_1417x:
case pll_1418x:
case pll_1051x:
case pll_1052x:
case pll_0818x:
case pll_0822x:
case pll_0516x:

2
drivers/clk/samsung/clk-pll.h
View File

@ -43,6 +43,8 @@ enum samsung_pll_type {
pll_0517x,
pll_0518x,
pll_531x,
pll_1051x,
pll_1052x,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \

2
drivers/clk/samsung/clk-s3c64xx.c
View File

@ -3,7 +3,7 @@
* Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
*
* Common Clock Framework support for all S3C64xx SoCs.
*/
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>

2
drivers/clk/samsung/clk-s5pv210-audss.c
View File

@ -8,7 +8,7 @@
* Author: Padmavathi Venna <padma.v@samsung.com>
*
* Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
*/
*/
#include <linux/io.h>
#include <linux/clk.h>

2
drivers/clk/samsung/clk.c
View File

@ -6,7 +6,7 @@
*
* This file includes utility functions to register clocks to common
* clock framework for Samsung platforms.
*/
*/
#include <linux/slab.h>
#include <linux/clkdev.h>

2
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
View File

@ -91,7 +91,7 @@ static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
},
};
static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
static const struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
[RST_BUS_R_PPU] = { 0x1ac, BIT(16) },

4
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View File

@ -1232,7 +1232,7 @@ static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
},
};
static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
static const struct ccu_reset_map sun20i_d1_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
[RST_BUS_DI] = { 0x62c, BIT(16) },
@ -1371,7 +1371,7 @@ static int sun20i_d1_ccu_probe(struct platform_device *pdev)
/* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
val &= ~BIT(1) | BIT(0);
val &= ~(BIT(1) | BIT(0));
writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
/* Force fanout-27M factor N to 0. */

2
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
View File

@ -1382,7 +1382,7 @@ static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
.num = CLK_NUMBER_SUN7I,
};
static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
static const struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
View File

@ -166,7 +166,7 @@ static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
[RST_R_APB1_PPU] = { 0x17c, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
View File

@ -1061,7 +1061,7 @@ static struct clk_hw_onecell_data sun50i_a100_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a100_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a100_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
View File

@ -858,7 +858,7 @@ static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a64_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

4
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View File

@ -179,7 +179,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
[RST_R_APB1_PWM] = { 0x13c, BIT(16) },
@ -190,7 +190,7 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
View File

@ -1076,7 +1076,7 @@ static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h6_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },

46
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
View File

@ -216,19 +216,29 @@ static struct ccu_nkmp pll_de_clk = {
};
/*
* TODO: Determine SDM settings for the audio PLL. The manual suggests
* PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
* for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
* pattern=0xe001288c for 22.5792 MHz.
* This clashes with our fixed PLL_POST_DIV_P.
* Sigma-delta modulation settings table obtained from the vendor SDK driver.
* There are additional M0 and M1 divider bits not modelled here, so forced to
* fixed values in the probe routine. Sigma-delta modulation allows providing a
* fractional-N divider in the PLL, to help reaching those specific
* frequencies with less error.
*/
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },
{ .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
};
#define SUN50I_H616_PLL_AUDIO_REG 0x078
static struct ccu_nm pll_audio_hs_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.m = _SUNXI_CCU_DIV(16, 6),
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
BIT(24), 0x178, BIT(31)),
.fixed_post_div = 2,
.common = {
.features = CCU_FEATURE_FIXED_POSTDIV |
CCU_FEATURE_SIGMA_DELTA_MOD,
.reg = 0x078,
.hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M",
&ccu_nm_ops,
@ -685,18 +695,20 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
};
/*
* The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
* rates can be set exactly in conjunction with sigma-delta modulation.
* The PLL_AUDIO_4X clock defaults to 24.5714 MHz according to the manual, with
* a final divider of 1. The 2X and 1X clocks use 2 and 4 respectively. The 1x
* clock is set to either 24576000 or 22579200 for 48Khz and 44.1Khz (and
* multiples).
*/
static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
clk_parent_pll_audio,
96, 1, CLK_SET_RATE_PARENT);
4, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
48, 1, CLK_SET_RATE_PARENT);
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
24, 1, CLK_SET_RATE_PARENT);
1, 1, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_periph0_parents[] = {
&pll_periph0_clk.common.hw
@ -990,7 +1002,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
@ -1136,12 +1148,14 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
}
/*
* Force the post-divider of pll-audio to 12 and the output divider
* of it to 2, so 24576000 and 22579200 rates can be set exactly.
* Set the output-divider for the pll-audio clocks (M0) to 2 and the
* input divider (M1) to 1 as recommended by the manual when using
* SDM.
*/
val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
val &= ~(GENMASK(21, 16) | BIT(0));
writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
val &= ~BIT(1);
val |= BIT(0);
writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
/*
* First clock parent (osc32K) is unusable for CEC. But since there

2
drivers/clk/sunxi-ng/ccu-sun5i.c
View File

@ -731,7 +731,7 @@ static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
static const struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },

2
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
View File

@ -1146,7 +1146,7 @@ static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
static const struct ccu_reset_map sun6i_a31_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
View File

@ -356,7 +356,7 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
const char *fw_name;
/* ext-osc32k was the only input clock in the old binding. */
fw_name = of_property_read_bool(dev->of_node, "clock-names")
fw_name = of_property_present(dev->of_node, "clock-names")
? "ext-osc32k" : NULL;
ext_osc32k_clk = devm_clk_get_optional(dev, fw_name);
if (IS_ERR(ext_osc32k_clk))

2
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
View File

@ -668,7 +668,7 @@ static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a23_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
View File

@ -712,7 +712,7 @@ static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a33_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
View File

@ -797,7 +797,7 @@ static struct clk_hw_onecell_data sun8i_a83t_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

8
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View File

@ -146,7 +146,7 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
.num = CLK_NUMBER_WITH_ROT,
};
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
static const struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
@ -156,7 +156,7 @@ static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
static const struct ccu_reset_map sun8i_h3_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
@ -166,14 +166,14 @@ static struct ccu_reset_map sun8i_h3_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
static struct ccu_reset_map sun50i_a64_de2_resets[] = {
static const struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
static const struct ccu_reset_map sun50i_h5_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },

4
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View File

@ -876,7 +876,7 @@ static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
.num = CLK_NUMBER_H5,
};
static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
static const struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
@ -939,7 +939,7 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_BUS_SCR0] = { 0x2d8, BIT(20) },
};
static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h5_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

6
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View File

@ -178,7 +178,7 @@ static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_RSB] = { 0xb0, BIT(3) },
@ -186,14 +186,14 @@ static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
static const struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_UART] = { 0xb0, BIT(4) },
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_RSB] = { 0xb0, BIT(3) },

2
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
View File

@ -1162,7 +1162,7 @@ static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
static const struct ccu_reset_map sun8i_r40_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

4
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@ -644,7 +644,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
.num = CLK_I2S0 + 1,
};
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
static const struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_MBUS] = { 0x0fc, BIT(31) },
@ -679,7 +679,7 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
};
static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
static const struct ccu_reset_map sun8i_v3_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_MBUS] = { 0x0fc, BIT(31) },

2
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
View File

@ -177,7 +177,7 @@ static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_de_resets[] = {
static const struct ccu_reset_map sun9i_a80_de_resets[] = {
[RST_FE0] = { 0x0c, BIT(0) },
[RST_FE1] = { 0x0c, BIT(1) },
[RST_FE2] = { 0x0c, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
View File

@ -68,7 +68,7 @@ static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_usb_resets[] = {
static const struct ccu_reset_map sun9i_a80_usb_resets[] = {
[RST_USB0_HCI] = { 0x0, BIT(17) },
[RST_USB1_HCI] = { 0x0, BIT(18) },
[RST_USB2_HCI] = { 0x0, BIT(19) },

2
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
View File

@ -1108,7 +1108,7 @@ static struct clk_hw_onecell_data sun9i_a80_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_ccu_resets[] = {
static const struct ccu_reset_map sun9i_a80_ccu_resets[] = {
/* AHB0 reset controls */
[RST_BUS_FD] = { 0x5a0, BIT(0) },
[RST_BUS_VE] = { 0x5a0, BIT(1) },

2
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
View File

@ -477,7 +477,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map suniv_ccu_resets[] = {
static const struct ccu_reset_map suniv_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },

2
drivers/clk/sunxi-ng/ccu_common.h
View File

@ -50,7 +50,7 @@ struct sunxi_ccu_desc {
struct clk_hw_onecell_data *hw_clks;
struct ccu_reset_map *resets;
const struct ccu_reset_map *resets;
unsigned long num_resets;
};

2
drivers/clk/sunxi-ng/ccu_reset.h
View File

@ -17,7 +17,7 @@ struct ccu_reset_map {
struct ccu_reset {
void __iomem *base;
struct ccu_reset_map *reset_map;
const struct ccu_reset_map *reset_map;
spinlock_t *lock;
struct reset_controller_dev rcdev;

15
drivers/reset/Kconfig
View File

@ -153,20 +153,6 @@ config RESET_MCHP_SPARX5
help
This driver supports switch core reset for the Microchip Sparx5 SoC.
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
default ARCH_MESON
help
This enables the reset driver for Amlogic Meson SoCs.
config RESET_MESON_AUDIO_ARB
tristate "Meson Audio Memory Arbiter Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
help
This enables the reset driver for Audio Memory Arbiter of
Amlogic's A113 based SoCs
config RESET_NPCM
bool "NPCM BMC Reset Driver" if COMPILE_TEST
default ARCH_NPCM
@ -357,6 +343,7 @@ config RESET_ZYNQMP
help
This enables the reset controller driver for Xilinx ZynqMP SoCs.
source "drivers/reset/amlogic/Kconfig"
source "drivers/reset/starfive/Kconfig"
source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig"

3
drivers/reset/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += core.o
obj-y += amlogic/
obj-y += hisilicon/
obj-y += starfive/
obj-y += sti/
@ -21,8 +22,6 @@ obj-$(CONFIG_RESET_K210) += reset-k210.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o

27
drivers/reset/amlogic/Kconfig Normal file
View File

@ -0,0 +1,27 @@
config RESET_MESON_COMMON
tristate
select REGMAP
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
default ARCH_MESON
select REGMAP_MMIO
select RESET_MESON_COMMON
help
This enables the reset driver for Amlogic SoCs.
config RESET_MESON_AUX
tristate "Meson Reset Auxiliary Driver"
depends on ARCH_MESON || COMPILE_TEST
select AUXILIARY_BUS
select RESET_MESON_COMMON
help
This enables the reset auxiliary driver for Amlogic SoCs.
config RESET_MESON_AUDIO_ARB
tristate "Meson Audio Memory Arbiter Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
help
This enables the reset driver for Audio Memory Arbiter of
Amlogic's A113 based SoCs

4
drivers/reset/amlogic/Makefile Normal file
View File

@ -0,0 +1,4 @@
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUX) += reset-meson-aux.o
obj-$(CONFIG_RESET_MESON_COMMON) += reset-meson-common.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o

0
drivers/reset/reset-meson-audio-arb.c → drivers/reset/amlogic/reset-meson-audio-arb.c
View File

136
drivers/reset/amlogic/reset-meson-aux.c Normal file
View File

@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Amlogic Meson Reset Auxiliary driver
*
* Copyright (c) 2024 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/auxiliary_bus.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "reset-meson.h"
#include <soc/amlogic/reset-meson-aux.h>
static DEFINE_IDA(meson_rst_aux_ida);
struct meson_reset_adev {
struct auxiliary_device adev;
struct regmap *map;
};
#define to_meson_reset_adev(_adev) \
container_of((_adev), struct meson_reset_adev, adev)
static const struct meson_reset_param meson_g12a_audio_param = {
.reset_ops = &meson_reset_toggle_ops,
.reset_num = 26,
.level_offset = 0x24,
};
static const struct meson_reset_param meson_sm1_audio_param = {
.reset_ops = &meson_reset_toggle_ops,
.reset_num = 39,
.level_offset = 0x28,
};
static const struct auxiliary_device_id meson_reset_aux_ids[] = {
{
.name = "axg-audio-clkc.rst-g12a",
.driver_data = (kernel_ulong_t)&meson_g12a_audio_param,
}, {
.name = "axg-audio-clkc.rst-sm1",
.driver_data = (kernel_ulong_t)&meson_sm1_audio_param,
}, {}
};
MODULE_DEVICE_TABLE(auxiliary, meson_reset_aux_ids);
static int meson_reset_aux_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
const struct meson_reset_param *param =
(const struct meson_reset_param *)(id->driver_data);
struct meson_reset_adev *raux =
to_meson_reset_adev(adev);
return meson_reset_controller_register(&adev->dev, raux->map, param);
}
static struct auxiliary_driver meson_reset_aux_driver = {
.probe = meson_reset_aux_probe,
.id_table = meson_reset_aux_ids,
};
module_auxiliary_driver(meson_reset_aux_driver);
static void meson_rst_aux_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
struct meson_reset_adev *raux =
to_meson_reset_adev(adev);
ida_free(&meson_rst_aux_ida, adev->id);
kfree(raux);
}
static void meson_rst_aux_unregister_adev(void *_adev)
{
struct auxiliary_device *adev = _adev;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
int devm_meson_rst_aux_register(struct device *dev,
struct regmap *map,
const char *adev_name)
{
struct meson_reset_adev *raux;
struct auxiliary_device *adev;
int ret;
raux = kzalloc(sizeof(*raux), GFP_KERNEL);
if (!raux)
return -ENOMEM;
ret = ida_alloc(&meson_rst_aux_ida, GFP_KERNEL);
if (ret < 0)
goto raux_free;
raux->map = map;
adev = &raux->adev;
adev->id = ret;
adev->name = adev_name;
adev->dev.parent = dev;
adev->dev.release = meson_rst_aux_release;
device_set_of_node_from_dev(&adev->dev, dev);
ret = auxiliary_device_init(adev);
if (ret)
goto ida_free;
ret = __auxiliary_device_add(adev, dev->driver->name);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(dev, meson_rst_aux_unregister_adev,
adev);
ida_free:
ida_free(&meson_rst_aux_ida, adev->id);
raux_free:
kfree(raux);
return ret;
}
EXPORT_SYMBOL_GPL(devm_meson_rst_aux_register);
MODULE_DESCRIPTION("Amlogic Meson Reset Auxiliary driver");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(MESON_RESET);

142
drivers/reset/amlogic/reset-meson-common.c Normal file
View File

@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Amlogic Meson Reset core functions
*
* Copyright (c) 2016-2024 BayLibre, SAS.
* Authors: Neil Armstrong <narmstrong@baylibre.com>
* Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include "reset-meson.h"
struct meson_reset {
const struct meson_reset_param *param;
struct reset_controller_dev rcdev;
struct regmap *map;
};
static void meson_reset_offset_and_bit(struct meson_reset *data,
unsigned long id,
unsigned int *offset,
unsigned int *bit)
{
unsigned int stride = regmap_get_reg_stride(data->map);
*offset = (id / (stride * BITS_PER_BYTE)) * stride;
*bit = id % (stride * BITS_PER_BYTE);
}
static int meson_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct meson_reset *data =
container_of(rcdev, struct meson_reset, rcdev);
unsigned int offset, bit;
meson_reset_offset_and_bit(data, id, &offset, &bit);
offset += data->param->reset_offset;
return regmap_write(data->map, offset, BIT(bit));
}
static int meson_reset_level(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct meson_reset *data =
container_of(rcdev, struct meson_reset, rcdev);
unsigned int offset, bit;
meson_reset_offset_and_bit(data, id, &offset, &bit);
offset += data->param->level_offset;
assert ^= data->param->level_low_reset;
return regmap_update_bits(data->map, offset,
BIT(bit), assert ? BIT(bit) : 0);
}
static int meson_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct meson_reset *data =
container_of(rcdev, struct meson_reset, rcdev);
unsigned int val, offset, bit;
meson_reset_offset_and_bit(data, id, &offset, &bit);
offset += data->param->level_offset;
regmap_read(data->map, offset, &val);
val = !!(BIT(bit) & val);
return val ^ data->param->level_low_reset;
}
static int meson_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return meson_reset_level(rcdev, id, true);
}
static int meson_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return meson_reset_level(rcdev, id, false);
}
static int meson_reset_level_toggle(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = meson_reset_assert(rcdev, id);
if (ret)
return ret;
return meson_reset_deassert(rcdev, id);
}
const struct reset_control_ops meson_reset_ops = {
.reset = meson_reset_reset,
.assert = meson_reset_assert,
.deassert = meson_reset_deassert,
.status = meson_reset_status,
};
EXPORT_SYMBOL_NS_GPL(meson_reset_ops, MESON_RESET);
const struct reset_control_ops meson_reset_toggle_ops = {
.reset = meson_reset_level_toggle,
.assert = meson_reset_assert,
.deassert = meson_reset_deassert,
.status = meson_reset_status,
};
EXPORT_SYMBOL_NS_GPL(meson_reset_toggle_ops, MESON_RESET);
int meson_reset_controller_register(struct device *dev, struct regmap *map,
const struct meson_reset_param *param)
{
struct meson_reset *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->param = param;
data->map = map;
data->rcdev.owner = dev->driver->owner;
data->rcdev.nr_resets = param->reset_num;
data->rcdev.ops = data->param->reset_ops;
data->rcdev.of_node = dev->of_node;
return devm_reset_controller_register(dev, &data->rcdev);
}
EXPORT_SYMBOL_NS_GPL(meson_reset_controller_register, MESON_RESET);
MODULE_DESCRIPTION("Amlogic Meson Reset Core function");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(MESON_RESET);

105
drivers/reset/amlogic/reset-meson.c Normal file
View File

@ -0,0 +1,105 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Amlogic Meson Reset Controller driver
*
* Copyright (c) 2016-2024 BayLibre, SAS.
* Authors: Neil Armstrong <narmstrong@baylibre.com>
* Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include "reset-meson.h"
static const struct meson_reset_param meson8b_param = {
.reset_ops = &meson_reset_ops,
.reset_num = 256,
.reset_offset = 0x0,
.level_offset = 0x7c,
.level_low_reset = true,
};
static const struct meson_reset_param meson_a1_param = {
.reset_ops = &meson_reset_ops,
.reset_num = 96,
.reset_offset = 0x0,
.level_offset = 0x40,
.level_low_reset = true,
};
static const struct meson_reset_param meson_s4_param = {
.reset_ops = &meson_reset_ops,
.reset_num = 192,
.reset_offset = 0x0,
.level_offset = 0x40,
.level_low_reset = true,
};
static const struct meson_reset_param t7_param = {
.reset_num = 224,
.reset_offset = 0x0,
.level_offset = 0x40,
.level_low_reset = true,
};
static const struct of_device_id meson_reset_dt_ids[] = {
{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
{ .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param},
{ .compatible = "amlogic,c3-reset", .data = &meson_s4_param},
{ .compatible = "amlogic,t7-reset", .data = &t7_param},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
static const struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static int meson_reset_probe(struct platform_device *pdev)
{
const struct meson_reset_param *param;
struct device *dev = &pdev->dev;
struct regmap *map;
void __iomem *base;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
param = device_get_match_data(dev);
if (!param)
return -ENODEV;
map = devm_regmap_init_mmio(dev, base, &regmap_config);
if (IS_ERR(map))
return dev_err_probe(dev, PTR_ERR(map),
"can't init regmap mmio region\n");
return meson_reset_controller_register(dev, map, param);
}
static struct platform_driver meson_reset_driver = {
.probe = meson_reset_probe,
.driver = {
.name = "meson_reset",
.of_match_table = meson_reset_dt_ids,
},
};
module_platform_driver(meson_reset_driver);
MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(MESON_RESET);

28
drivers/reset/amlogic/reset-meson.h Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (c) 2024 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __MESON_RESET_H
#define __MESON_RESET_H
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
struct meson_reset_param {
const struct reset_control_ops *reset_ops;
unsigned int reset_num;
unsigned int reset_offset;
unsigned int level_offset;
bool level_low_reset;
};
int meson_reset_controller_register(struct device *dev, struct regmap *map,
const struct meson_reset_param *param);
extern const struct reset_control_ops meson_reset_ops;
extern const struct reset_control_ops meson_reset_toggle_ops;
#endif /* __MESON_RESET_H */

159
drivers/reset/reset-meson.c
View File

@ -1,159 +0,0 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Amlogic Meson Reset Controller driver
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/types.h>
#define BITS_PER_REG 32
struct meson_reset_param {
int reg_count;
int level_offset;
};
struct meson_reset {
void __iomem *reg_base;
const struct meson_reset_param *param;
struct reset_controller_dev rcdev;
spinlock_t lock;
};
static int meson_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct meson_reset *data =
container_of(rcdev, struct meson_reset, rcdev);
unsigned int bank = id / BITS_PER_REG;
unsigned int offset = id % BITS_PER_REG;
void __iomem *reg_addr = data->reg_base + (bank << 2);
writel(BIT(offset), reg_addr);
return 0;
}
static int meson_reset_level(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct meson_reset *data =
container_of(rcdev, struct meson_reset, rcdev);
unsigned int bank = id / BITS_PER_REG;
unsigned int offset = id % BITS_PER_REG;
void __iomem *reg_addr;
unsigned long flags;
u32 reg;
reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
spin_lock_irqsave(&data->lock, flags);
reg = readl(reg_addr);
if (assert)
writel(reg & ~BIT(offset), reg_addr);
else
writel(reg | BIT(offset), reg_addr);
spin_unlock_irqrestore(&data->lock, flags);
return 0;
}
static int meson_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return meson_reset_level(rcdev, id, true);
}
static int meson_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return meson_reset_level(rcdev, id, false);
}
static const struct reset_control_ops meson_reset_ops = {
.reset = meson_reset_reset,
.assert = meson_reset_assert,
.deassert = meson_reset_deassert,
};
static const struct meson_reset_param meson8b_param = {
.reg_count = 8,
.level_offset = 0x7c,
};
static const struct meson_reset_param meson_a1_param = {
.reg_count = 3,
.level_offset = 0x40,
};
static const struct meson_reset_param meson_s4_param = {
.reg_count = 6,
.level_offset = 0x40,
};
static const struct meson_reset_param t7_param = {
.reg_count = 7,
.level_offset = 0x40,
};
static const struct of_device_id meson_reset_dt_ids[] = {
{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
{ .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param},
{ .compatible = "amlogic,c3-reset", .data = &meson_s4_param},
{ .compatible = "amlogic,t7-reset", .data = &t7_param},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
static int meson_reset_probe(struct platform_device *pdev)
{
struct meson_reset *data;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
data->param = of_device_get_match_data(&pdev->dev);
if (!data->param)
return -ENODEV;
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
data->rcdev.ops = &meson_reset_ops;
data->rcdev.of_node = pdev->dev.of_node;
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}
static struct platform_driver meson_reset_driver = {
.probe = meson_reset_probe,
.driver = {
.name = "meson_reset",
.of_match_table = meson_reset_dt_ids,
},
};
module_platform_driver(meson_reset_driver);
MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");

7
include/dt-bindings/clock/fsd-clk.h
View File

@ -28,7 +28,6 @@
#define DOUT_CMU_IMEM_ACLK 13
#define DOUT_CMU_IMEM_DMACLK 14
#define GAT_CMU_FSYS0_SHARED0DIV4 15
#define CMU_NR_CLK 16
/* PERIC */
#define PERIC_SCLK_UART0 1
@ -76,7 +75,6 @@
#define PERIC_EQOS_PHYRXCLK_MUX 43
#define PERIC_EQOS_PHYRXCLK 44
#define PERIC_DOUT_RGMII_CLK 45
#define PERIC_NR_CLK 46
/* FSYS0 */
#define UFS0_MPHY_REFCLK_IXTAL24 1
@ -101,7 +99,6 @@
#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
#define FSYS0_NR_CLK 23
/* FSYS1 */
#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
@ -112,7 +109,6 @@
#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
#define FSYS1_NR_CLK 9
/* IMEM */
#define IMEM_DMA0_IPCLKPORT_ACLK 1
@ -126,11 +122,9 @@
#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
#define IMEM_NR_CLK 12
/* MFC */
#define MFC_MFC_IPCLKPORT_ACLK 1
#define MFC_NR_CLK 2
/* CAM_CSI */
#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
@ -145,6 +139,5 @@
#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
#define CAM_CSI_NR_CLK 13
#endif /*_DT_BINDINGS_CLOCK_FSD_H */

6
include/dt-bindings/clock/imx93-clock.h
View File

@ -204,6 +204,10 @@
#define IMX93_CLK_A55_SEL 199
#define IMX93_CLK_A55_CORE 200
#define IMX93_CLK_PDM_IPG 201
#define IMX93_CLK_END 202
#define IMX91_CLK_ENET1_QOS_TSN 202
#define IMX91_CLK_ENET_TIMER 203
#define IMX91_CLK_ENET2_REGULAR 204
#define IMX91_CLK_ENET2_REGULAR_GATE 205
#define IMX91_CLK_ENET1_QOS_TSN_GATE 206
#endif

453
include/dt-bindings/clock/samsung,exynos8895.h Normal file
View File

@ -0,0 +1,453 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
*
* Device Tree binding constants for Exynos8895 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS8895_H
#define _DT_BINDINGS_CLOCK_EXYNOS8895_H
/* CMU_TOP */
#define CLK_FOUT_SHARED0_PLL 1
#define CLK_FOUT_SHARED1_PLL 2
#define CLK_FOUT_SHARED2_PLL 3
#define CLK_FOUT_SHARED3_PLL 4
#define CLK_FOUT_SHARED4_PLL 5
#define CLK_MOUT_PLL_SHARED0 6
#define CLK_MOUT_PLL_SHARED1 7
#define CLK_MOUT_PLL_SHARED2 8
#define CLK_MOUT_PLL_SHARED3 9
#define CLK_MOUT_PLL_SHARED4 10
#define CLK_MOUT_CP2AP_MIF_CLK_USER 11
#define CLK_MOUT_CMU_ABOX_CPUABOX 12
#define CLK_MOUT_CMU_APM_BUS 13
#define CLK_MOUT_CMU_BUS1_BUS 14
#define CLK_MOUT_CMU_BUSC_BUS 15
#define CLK_MOUT_CMU_BUSC_BUSPHSI2C 16
#define CLK_MOUT_CMU_CAM_BUS 17
#define CLK_MOUT_CMU_CAM_TPU0 18
#define CLK_MOUT_CMU_CAM_TPU1 19
#define CLK_MOUT_CMU_CAM_VRA 20
#define CLK_MOUT_CMU_CIS_CLK0 21
#define CLK_MOUT_CMU_CIS_CLK1 22
#define CLK_MOUT_CMU_CIS_CLK2 23
#define CLK_MOUT_CMU_CIS_CLK3 24
#define CLK_MOUT_CMU_CORE_BUS 25
#define CLK_MOUT_CMU_CPUCL0_SWITCH 26
#define CLK_MOUT_CMU_CPUCL1_SWITCH 27
#define CLK_MOUT_CMU_DBG_BUS 28
#define CLK_MOUT_CMU_DCAM_BUS 29
#define CLK_MOUT_CMU_DCAM_IMGD 30
#define CLK_MOUT_CMU_DPU_BUS 31
#define CLK_MOUT_CMU_DROOPDETECTOR 32
#define CLK_MOUT_CMU_DSP_BUS 33
#define CLK_MOUT_CMU_FSYS0_BUS 34
#define CLK_MOUT_CMU_FSYS0_DPGTC 35
#define CLK_MOUT_CMU_FSYS0_MMC_EMBD 36
#define CLK_MOUT_CMU_FSYS0_UFS_EMBD 37
#define CLK_MOUT_CMU_FSYS0_USBDRD30 38
#define CLK_MOUT_CMU_FSYS1_BUS 39
#define CLK_MOUT_CMU_FSYS1_MMC_CARD 40
#define CLK_MOUT_CMU_FSYS1_PCIE 41
#define CLK_MOUT_CMU_FSYS1_UFS_CARD 42
#define CLK_MOUT_CMU_G2D_G2D 43
#define CLK_MOUT_CMU_G2D_JPEG 44
#define CLK_MOUT_CMU_HPM 45
#define CLK_MOUT_CMU_IMEM_BUS 46
#define CLK_MOUT_CMU_ISPHQ_BUS 47
#define CLK_MOUT_CMU_ISPLP_BUS 48
#define CLK_MOUT_CMU_IVA_BUS 49
#define CLK_MOUT_CMU_MFC_BUS 50
#define CLK_MOUT_CMU_MIF_SWITCH 51
#define CLK_MOUT_CMU_PERIC0_BUS 52
#define CLK_MOUT_CMU_PERIC0_UART_DBG 53
#define CLK_MOUT_CMU_PERIC0_USI00 54
#define CLK_MOUT_CMU_PERIC0_USI01 55
#define CLK_MOUT_CMU_PERIC0_USI02 56
#define CLK_MOUT_CMU_PERIC0_USI03 57
#define CLK_MOUT_CMU_PERIC1_BUS 58
#define CLK_MOUT_CMU_PERIC1_SPEEDY2 59
#define CLK_MOUT_CMU_PERIC1_SPI_CAM0 60
#define CLK_MOUT_CMU_PERIC1_SPI_CAM1 61
#define CLK_MOUT_CMU_PERIC1_UART_BT 62
#define CLK_MOUT_CMU_PERIC1_USI04 63
#define CLK_MOUT_CMU_PERIC1_USI05 64
#define CLK_MOUT_CMU_PERIC1_USI06 65
#define CLK_MOUT_CMU_PERIC1_USI07 66
#define CLK_MOUT_CMU_PERIC1_USI08 67
#define CLK_MOUT_CMU_PERIC1_USI09 68
#define CLK_MOUT_CMU_PERIC1_USI10 69
#define CLK_MOUT_CMU_PERIC1_USI11 70
#define CLK_MOUT_CMU_PERIC1_USI12 71
#define CLK_MOUT_CMU_PERIC1_USI13 72
#define CLK_MOUT_CMU_PERIS_BUS 73
#define CLK_MOUT_CMU_SRDZ_BUS 74
#define CLK_MOUT_CMU_SRDZ_IMGD 75
#define CLK_MOUT_CMU_VPU_BUS 76
#define CLK_DOUT_CMU_ABOX_CPUABOX 77
#define CLK_DOUT_CMU_APM_BUS 78
#define CLK_DOUT_CMU_BUS1_BUS 79
#define CLK_DOUT_CMU_BUSC_BUS 80
#define CLK_DOUT_CMU_BUSC_BUSPHSI2C 81
#define CLK_DOUT_CMU_CAM_BUS 82
#define CLK_DOUT_CMU_CAM_TPU0 83
#define CLK_DOUT_CMU_CAM_TPU1 84
#define CLK_DOUT_CMU_CAM_VRA 85
#define CLK_DOUT_CMU_CIS_CLK0 86
#define CLK_DOUT_CMU_CIS_CLK1 87
#define CLK_DOUT_CMU_CIS_CLK2 88
#define CLK_DOUT_CMU_CIS_CLK3 89
#define CLK_DOUT_CMU_CORE_BUS 90
#define CLK_DOUT_CMU_CPUCL0_SWITCH 91
#define CLK_DOUT_CMU_CPUCL1_SWITCH 92
#define CLK_DOUT_CMU_DBG_BUS 93
#define CLK_DOUT_CMU_DCAM_BUS 94
#define CLK_DOUT_CMU_DCAM_IMGD 95
#define CLK_DOUT_CMU_DPU_BUS 96
#define CLK_DOUT_CMU_DSP_BUS 97
#define CLK_DOUT_CMU_FSYS0_BUS 98
#define CLK_DOUT_CMU_FSYS0_DPGTC 99
#define CLK_DOUT_CMU_FSYS0_MMC_EMBD 100
#define CLK_DOUT_CMU_FSYS0_UFS_EMBD 101
#define CLK_DOUT_CMU_FSYS0_USBDRD30 102
#define CLK_DOUT_CMU_FSYS1_BUS 103
#define CLK_DOUT_CMU_FSYS1_MMC_CARD 104
#define CLK_DOUT_CMU_FSYS1_UFS_CARD 105
#define CLK_DOUT_CMU_G2D_G2D 106
#define CLK_DOUT_CMU_G2D_JPEG 107
#define CLK_DOUT_CMU_G3D_SWITCH 108
#define CLK_DOUT_CMU_HPM 109
#define CLK_DOUT_CMU_IMEM_BUS 110
#define CLK_DOUT_CMU_ISPHQ_BUS 111
#define CLK_DOUT_CMU_ISPLP_BUS 112
#define CLK_DOUT_CMU_IVA_BUS 113
#define CLK_DOUT_CMU_MFC_BUS 114
#define CLK_DOUT_CMU_MODEM_SHARED0 115
#define CLK_DOUT_CMU_MODEM_SHARED1 116
#define CLK_DOUT_CMU_PERIC0_BUS 117
#define CLK_DOUT_CMU_PERIC0_UART_DBG 118
#define CLK_DOUT_CMU_PERIC0_USI00 119
#define CLK_DOUT_CMU_PERIC0_USI01 120
#define CLK_DOUT_CMU_PERIC0_USI02 121
#define CLK_DOUT_CMU_PERIC0_USI03 122
#define CLK_DOUT_CMU_PERIC1_BUS 123
#define CLK_DOUT_CMU_PERIC1_SPEEDY2 124
#define CLK_DOUT_CMU_PERIC1_SPI_CAM0 125
#define CLK_DOUT_CMU_PERIC1_SPI_CAM1 126
#define CLK_DOUT_CMU_PERIC1_UART_BT 127
#define CLK_DOUT_CMU_PERIC1_USI04 128
#define CLK_DOUT_CMU_PERIC1_USI05 129
#define CLK_DOUT_CMU_PERIC1_USI06 130
#define CLK_DOUT_CMU_PERIC1_USI07 131
#define CLK_DOUT_CMU_PERIC1_USI08 132
#define CLK_DOUT_CMU_PERIC1_USI09 133
#define CLK_DOUT_CMU_PERIC1_USI10 134
#define CLK_DOUT_CMU_PERIC1_USI11 135
#define CLK_DOUT_CMU_PERIC1_USI12 136
#define CLK_DOUT_CMU_PERIC1_USI13 137
#define CLK_DOUT_CMU_PERIS_BUS 138
#define CLK_DOUT_CMU_SRDZ_BUS 139
#define CLK_DOUT_CMU_SRDZ_IMGD 140
#define CLK_DOUT_CMU_VPU_BUS 141
#define CLK_DOUT_CMU_SHARED0_DIV2 142
#define CLK_DOUT_CMU_SHARED0_DIV4 143
#define CLK_DOUT_CMU_SHARED1_DIV2 144
#define CLK_DOUT_CMU_SHARED1_DIV4 145
#define CLK_DOUT_CMU_SHARED2_DIV2 146
#define CLK_DOUT_CMU_SHARED3_DIV2 147
#define CLK_DOUT_CMU_SHARED4_DIV2 148
#define CLK_DOUT_CMU_FSYS1_PCIE 149
#define CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2 150
#define CLK_DOUT_CMU_CMU_OTP 151
#define CLK_GOUT_CMU_DROOPDETECTOR 152
#define CLK_GOUT_CMU_MIF_SWITCH 153
#define CLK_GOUT_CMU_ABOX_CPUABOX 154
#define CLK_GOUT_CMU_APM_BUS 155
#define CLK_GOUT_CMU_BUS1_BUS 156
#define CLK_GOUT_CMU_BUSC_BUS 157
#define CLK_GOUT_CMU_BUSC_BUSPHSI2C 158
#define CLK_GOUT_CMU_CAM_BUS 159
#define CLK_GOUT_CMU_CAM_TPU0 160
#define CLK_GOUT_CMU_CAM_TPU1 161
#define CLK_GOUT_CMU_CAM_VRA 162
#define CLK_GOUT_CMU_CIS_CLK0 163
#define CLK_GOUT_CMU_CIS_CLK1 164
#define CLK_GOUT_CMU_CIS_CLK2 165
#define CLK_GOUT_CMU_CIS_CLK3 166
#define CLK_GOUT_CMU_CORE_BUS 167
#define CLK_GOUT_CMU_CPUCL0_SWITCH 168
#define CLK_GOUT_CMU_CPUCL1_SWITCH 169
#define CLK_GOUT_CMU_DBG_BUS 170
#define CLK_GOUT_CMU_DCAM_BUS 171
#define CLK_GOUT_CMU_DCAM_IMGD 172
#define CLK_GOUT_CMU_DPU_BUS 173
#define CLK_GOUT_CMU_DSP_BUS 174
#define CLK_GOUT_CMU_FSYS0_BUS 175
#define CLK_GOUT_CMU_FSYS0_DPGTC 176
#define CLK_GOUT_CMU_FSYS0_MMC_EMBD 177
#define CLK_GOUT_CMU_FSYS0_UFS_EMBD 178
#define CLK_GOUT_CMU_FSYS0_USBDRD30 179
#define CLK_GOUT_CMU_FSYS1_BUS 180
#define CLK_GOUT_CMU_FSYS1_MMC_CARD 181
#define CLK_GOUT_CMU_FSYS1_PCIE 182
#define CLK_GOUT_CMU_FSYS1_UFS_CARD 183
#define CLK_GOUT_CMU_G2D_G2D 184
#define CLK_GOUT_CMU_G2D_JPEG 185
#define CLK_GOUT_CMU_G3D_SWITCH 186
#define CLK_GOUT_CMU_HPM 187
#define CLK_GOUT_CMU_IMEM_BUS 188
#define CLK_GOUT_CMU_ISPHQ_BUS 189
#define CLK_GOUT_CMU_ISPLP_BUS 190
#define CLK_GOUT_CMU_IVA_BUS 191
#define CLK_GOUT_CMU_MFC_BUS 192
#define CLK_GOUT_CMU_MODEM_SHARED0 193
#define CLK_GOUT_CMU_MODEM_SHARED1 194
#define CLK_GOUT_CMU_PERIC0_BUS 195
#define CLK_GOUT_CMU_PERIC0_UART_DBG 196
#define CLK_GOUT_CMU_PERIC0_USI00 197
#define CLK_GOUT_CMU_PERIC0_USI01 198
#define CLK_GOUT_CMU_PERIC0_USI02 199
#define CLK_GOUT_CMU_PERIC0_USI03 200
#define CLK_GOUT_CMU_PERIC1_BUS 201
#define CLK_GOUT_CMU_PERIC1_SPEEDY2 202
#define CLK_GOUT_CMU_PERIC1_SPI_CAM0 203
#define CLK_GOUT_CMU_PERIC1_SPI_CAM1 204
#define CLK_GOUT_CMU_PERIC1_UART_BT 205
#define CLK_GOUT_CMU_PERIC1_USI04 206
#define CLK_GOUT_CMU_PERIC1_USI05 207
#define CLK_GOUT_CMU_PERIC1_USI06 208
#define CLK_GOUT_CMU_PERIC1_USI07 209
#define CLK_GOUT_CMU_PERIC1_USI08 210
#define CLK_GOUT_CMU_PERIC1_USI09 211
#define CLK_GOUT_CMU_PERIC1_USI10 212
#define CLK_GOUT_CMU_PERIC1_USI11 213
#define CLK_GOUT_CMU_PERIC1_USI12 214
#define CLK_GOUT_CMU_PERIC1_USI13 215
#define CLK_GOUT_CMU_PERIS_BUS 216
#define CLK_GOUT_CMU_SRDZ_BUS 217
#define CLK_GOUT_CMU_SRDZ_IMGD 218
#define CLK_GOUT_CMU_VPU_BUS 219
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
#define CLK_MOUT_PERIS_GIC 2
#define CLK_GOUT_PERIS_CMU_PERIS_PCLK 3
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 4
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS 5
#define CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK 6
#define CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK 7
#define CLK_GOUT_PERIS_BUSIF_TMU_PCLK 8
#define CLK_GOUT_PERIS_GIC_CLK 9
#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK 10
#define CLK_GOUT_PERIS_MCT_PCLK 11
#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 12
#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 13
#define CLK_GOUT_PERIS_PMU_PERIS_PCLK 14
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK 15
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK 16
#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 17
#define CLK_GOUT_PERIS_TZPC00_PCLK 18
#define CLK_GOUT_PERIS_TZPC01_PCLK 19
#define CLK_GOUT_PERIS_TZPC02_PCLK 20
#define CLK_GOUT_PERIS_TZPC03_PCLK 21
#define CLK_GOUT_PERIS_TZPC04_PCLK 22
#define CLK_GOUT_PERIS_TZPC05_PCLK 23
#define CLK_GOUT_PERIS_TZPC06_PCLK 24
#define CLK_GOUT_PERIS_TZPC07_PCLK 25
#define CLK_GOUT_PERIS_TZPC08_PCLK 26
#define CLK_GOUT_PERIS_TZPC09_PCLK 27
#define CLK_GOUT_PERIS_TZPC10_PCLK 28
#define CLK_GOUT_PERIS_TZPC11_PCLK 29
#define CLK_GOUT_PERIS_TZPC12_PCLK 30
#define CLK_GOUT_PERIS_TZPC13_PCLK 31
#define CLK_GOUT_PERIS_TZPC14_PCLK 32
#define CLK_GOUT_PERIS_TZPC15_PCLK 33
#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 34
#define CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK 35
#define CLK_GOUT_PERIS_XIU_P_PERIS_ACLK 36
/* CMU_FSYS0 */
#define CLK_MOUT_FSYS0_BUS_USER 1
#define CLK_MOUT_FSYS0_DPGTC_USER 2
#define CLK_MOUT_FSYS0_MMC_EMBD_USER 3
#define CLK_MOUT_FSYS0_UFS_EMBD_USER 4
#define CLK_MOUT_FSYS0_USBDRD30_USER 5
#define CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK 6
#define CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK 7
#define CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK 8
#define CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK 9
#define CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK 10
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK 11
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK 12
#define CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK 13
#define CLK_GOUT_FSYS0_DP_LINK_I_PCLK 14
#define CLK_GOUT_FSYS0_ETR_MIU_I_ACLK 15
#define CLK_GOUT_FSYS0_ETR_MIU_I_PCLK 16
#define CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK 17
#define CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK 18
#define CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK 19
#define CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK 20
#define CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK 21
#define CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK 22
#define CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN 23
#define CLK_GOUT_FSYS0_PMU_FSYS0_PCLK 24
#define CLK_GOUT_FSYS0_BCM_FSYS0_ACLK 25
#define CLK_GOUT_FSYS0_BCM_FSYS0_PCLK 26
#define CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK 27
#define CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK 28
#define CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK 29
#define CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO 30
#define CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK 31
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK 32
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK 33
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK 34
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK 35
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK 36
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK 37
#define CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK 38
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK 39
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK 40
#define CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK 41
/* CMU_FSYS1 */
#define CLK_MOUT_FSYS1_BUS_USER 1
#define CLK_MOUT_FSYS1_MMC_CARD_USER 2
#define CLK_MOUT_FSYS1_PCIE_USER 3
#define CLK_MOUT_FSYS1_UFS_CARD_USER 4
#define CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN 5
#define CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM 6
#define CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK 7
#define CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK 8
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK 9
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK 10
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK 11
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK 12
#define CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK 13
#define CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK 14
#define CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK 15
#define CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK 16
#define CLK_GOUT_FSYS1_MMC_CARD_I_ACLK 17
#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 18
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0 19
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1 20
#define CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 21
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0 22
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1 23
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 24
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 25
#define CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 26
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0 27
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1 28
#define CLK_GOUT_FSYS1_PMU_FSYS1_PCLK 29
#define CLK_GOUT_FSYS1_BCM_FSYS1_ACLK 30
#define CLK_GOUT_FSYS1_BCM_FSYS1_PCLK 31
#define CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK 32
#define CLK_GOUT_FSYS1_RTIC_I_ACLK 33
#define CLK_GOUT_FSYS1_RTIC_I_PCLK 34
#define CLK_GOUT_FSYS1_SSS_I_ACLK 35
#define CLK_GOUT_FSYS1_SSS_I_PCLK 36
#define CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK 37
#define CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK 38
#define CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK 39
#define CLK_GOUT_FSYS1_UFS_CARD_I_ACLK 40
#define CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO 41
#define CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK 42
#define CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK 43
#define CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK 44
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_BUS_USER 1
#define CLK_MOUT_PERIC0_UART_DBG_USER 2
#define CLK_MOUT_PERIC0_USI00_USER 3
#define CLK_MOUT_PERIC0_USI01_USER 4
#define CLK_MOUT_PERIC0_USI02_USER 5
#define CLK_MOUT_PERIC0_USI03_USER 6
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 7
#define CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK 8
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 9
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 10
#define CLK_GOUT_PERIC0_PMU_PERIC0_PCLK 11
#define CLK_GOUT_PERIC0_PWM_I_PCLK_S0 12
#define CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK 13
#define CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK 14
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 15
#define CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK 16
#define CLK_GOUT_PERIC0_UART_DBG_PCLK 17
#define CLK_GOUT_PERIC0_USI00_I_PCLK 18
#define CLK_GOUT_PERIC0_USI00_I_SCLK_USI 19
#define CLK_GOUT_PERIC0_USI01_I_PCLK 20
#define CLK_GOUT_PERIC0_USI01_I_SCLK_USI 21
#define CLK_GOUT_PERIC0_USI02_I_PCLK 22
#define CLK_GOUT_PERIC0_USI02_I_SCLK_USI 23
#define CLK_GOUT_PERIC0_USI03_I_PCLK 24
#define CLK_GOUT_PERIC0_USI03_I_SCLK_USI 25
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
#define CLK_MOUT_PERIC1_SPEEDY2_USER 2
#define CLK_MOUT_PERIC1_SPI_CAM0_USER 3
#define CLK_MOUT_PERIC1_SPI_CAM1_USER 4
#define CLK_MOUT_PERIC1_UART_BT_USER 5
#define CLK_MOUT_PERIC1_USI04_USER 6
#define CLK_MOUT_PERIC1_USI05_USER 7
#define CLK_MOUT_PERIC1_USI06_USER 8
#define CLK_MOUT_PERIC1_USI07_USER 9
#define CLK_MOUT_PERIC1_USI08_USER 10
#define CLK_MOUT_PERIC1_USI09_USER 11
#define CLK_MOUT_PERIC1_USI10_USER 12
#define CLK_MOUT_PERIC1_USI11_USER 13
#define CLK_MOUT_PERIC1_USI12_USER 14
#define CLK_MOUT_PERIC1_USI13_USER 15
#define CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK 16
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK 17
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK 18
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK 19
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK 20
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 21
#define CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK 22
#define CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK 23
#define CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK 24
#define CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK 25
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 26
#define CLK_GOUT_PERIC1_PMU_PERIC1_PCLK 27
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK 28
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK 29
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK 30
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK 31
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK 32
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK 33
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK 34
#define CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK 35
#define CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK 36
#define CLK_GOUT_PERIC1_SPI_CAM0_PCLK 37
#define CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK 38
#define CLK_GOUT_PERIC1_SPI_CAM1_PCLK 39
#define CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK 40
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 41
#define CLK_GOUT_PERIC1_UART_BT_EXT_UCLK 42
#define CLK_GOUT_PERIC1_UART_BT_PCLK 43
#define CLK_GOUT_PERIC1_USI04_I_PCLK 44
#define CLK_GOUT_PERIC1_USI04_I_SCLK_USI 45
#define CLK_GOUT_PERIC1_USI05_I_PCLK 46
#define CLK_GOUT_PERIC1_USI05_I_SCLK_USI 47
#define CLK_GOUT_PERIC1_USI06_I_PCLK 48
#define CLK_GOUT_PERIC1_USI06_I_SCLK_USI 49
#define CLK_GOUT_PERIC1_USI07_I_PCLK 50
#define CLK_GOUT_PERIC1_USI07_I_SCLK_USI 51
#define CLK_GOUT_PERIC1_USI08_I_PCLK 52
#define CLK_GOUT_PERIC1_USI08_I_SCLK_USI 53
#define CLK_GOUT_PERIC1_USI09_I_PCLK 54
#define CLK_GOUT_PERIC1_USI09_I_SCLK_USI 55
#define CLK_GOUT_PERIC1_USI10_I_PCLK 56
#define CLK_GOUT_PERIC1_USI10_I_SCLK_USI 57
#define CLK_GOUT_PERIC1_USI11_I_PCLK 58
#define CLK_GOUT_PERIC1_USI11_I_SCLK_USI 59
#define CLK_GOUT_PERIC1_USI12_I_PCLK 60
#define CLK_GOUT_PERIC1_USI12_I_SCLK_USI 61
#define CLK_GOUT_PERIC1_USI13_I_PCLK 62
#define CLK_GOUT_PERIC1_USI13_I_SCLK_USI 63
#define CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK 64
#endif /* _DT_BINDINGS_CLOCK_EXYNOS8895_H */

47
include/dt-bindings/clock/samsung,exynosautov920.h
View File

@ -160,6 +160,7 @@
#define DOUT_CLKCMU_SNW_NOC 144
#define DOUT_CLKCMU_SSP_NOC 145
#define DOUT_CLKCMU_TAA_NOC 146
#define DOUT_TCXO_DIV2 147
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_IP_USER 1
@ -188,4 +189,50 @@
#define CLK_DOUT_PERIC0_USI_I2C 23
#define CLK_DOUT_PERIC0_I3C 24
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_IP_USER 1
#define CLK_MOUT_PERIC1_NOC_USER 2
#define CLK_MOUT_PERIC1_USI09_USI 3
#define CLK_MOUT_PERIC1_USI10_USI 4
#define CLK_MOUT_PERIC1_USI11_USI 5
#define CLK_MOUT_PERIC1_USI12_USI 6
#define CLK_MOUT_PERIC1_USI13_USI 7
#define CLK_MOUT_PERIC1_USI14_USI 8
#define CLK_MOUT_PERIC1_USI15_USI 9
#define CLK_MOUT_PERIC1_USI16_USI 10
#define CLK_MOUT_PERIC1_USI17_USI 11
#define CLK_MOUT_PERIC1_USI_I2C 12
#define CLK_MOUT_PERIC1_I3C 13
#define CLK_DOUT_PERIC1_USI09_USI 14
#define CLK_DOUT_PERIC1_USI10_USI 15
#define CLK_DOUT_PERIC1_USI11_USI 16
#define CLK_DOUT_PERIC1_USI12_USI 17
#define CLK_DOUT_PERIC1_USI13_USI 18
#define CLK_DOUT_PERIC1_USI14_USI 19
#define CLK_DOUT_PERIC1_USI15_USI 20
#define CLK_DOUT_PERIC1_USI16_USI 21
#define CLK_DOUT_PERIC1_USI17_USI 22
#define CLK_DOUT_PERIC1_USI_I2C 23
#define CLK_DOUT_PERIC1_I3C 24
/* CMU_MISC */
#define CLK_MOUT_MISC_NOC_USER 1
#define CLK_MOUT_MISC_GIC 2
#define CLK_DOUT_MISC_OTP 3
#define CLK_DOUT_MISC_NOCP 4
#define CLK_DOUT_MISC_OSC_DIV2 5
/* CMU_HSI0 */
#define CLK_MOUT_HSI0_NOC_USER 1
#define CLK_DOUT_HSI0_PCIE_APB 2
/* CMU_HSI1 */
#define CLK_MOUT_HSI1_MMC_CARD_USER 1
#define CLK_MOUT_HSI1_NOC_USER 2
#define CLK_MOUT_HSI1_USBDRD_USER 3
#define CLK_MOUT_HSI1_USBDRD 4
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */

23
include/soc/amlogic/reset-meson-aux.h Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SOC_RESET_MESON_AUX_H
#define __SOC_RESET_MESON_AUX_H
#include <linux/err.h>
struct device;
struct regmap;
#if IS_ENABLED(CONFIG_RESET_MESON_AUX)
int devm_meson_rst_aux_register(struct device *dev,
struct regmap *map,
const char *adev_name);
#else
static inline int devm_meson_rst_aux_register(struct device *dev,
struct regmap *map,
const char *adev_name)
{
return 0;
}
#endif
#endif /* __SOC_RESET_MESON_AUX_H */