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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ASoC: stm32: i2s: add stm32mp25 support
Merge series from Olivier Moysan <olivier.moysan@foss.st.com>: Update STM32 I2S driver and binding to support STM32MP25 SoCs.
This commit is contained in:
Mark Brown
commit
125d0f698a
@ -13,13 +13,11 @@ description:
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The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
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Only some SPI instances support I2S.
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allOf:
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- $ref: dai-common.yaml#
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properties:
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compatible:
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enum:
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- st,stm32h7-i2s
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- st,stm32mp25-i2s
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"#sound-dai-cells":
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const: 0
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@ -33,6 +31,7 @@ properties:
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- description: clock feeding the internal clock generator.
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- description: I2S parent clock for sampling rates multiple of 8kHz.
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- description: I2S parent clock for sampling rates multiple of 11.025kHz.
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minItems: 2
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clock-names:
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items:
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@ -40,6 +39,7 @@ properties:
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- const: i2sclk
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- const: x8k
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- const: x11k
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minItems: 2
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interrupts:
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maxItems: 1
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@ -79,6 +79,36 @@ required:
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- dmas
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- dma-names
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allOf:
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- $ref: dai-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32h7-i2s
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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minItems: 4
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp25-i2s
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then:
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properties:
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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unevaluatedProperties: false
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examples:
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@ -200,10 +200,13 @@ enum i2s_datlen {
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#define STM32_I2S_NAME_LEN 32
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#define STM32_I2S_RATE_11K 11025
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#define STM32_I2S_MAX_SAMPLE_RATE_8K 192000
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#define STM32_I2S_MAX_SAMPLE_RATE_11K 176400
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#define STM32_I2S_CLK_RATE_TOLERANCE 1000 /* ppm */
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/**
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* struct stm32_i2s_data - private data of I2S
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* @regmap_conf: I2S register map configuration pointer
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* @conf: I2S configuration pointer
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* @regmap: I2S register map pointer
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* @pdev: device data pointer
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* @dai_drv: DAI driver pointer
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@ -224,11 +227,14 @@ enum i2s_datlen {
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* @divider: prescaler division ratio
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* @div: prescaler div field
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* @odd: prescaler odd field
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* @i2s_clk_flg: flag set while exclusivity on I2S kernel clock is active
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* @refcount: keep count of opened streams on I2S
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* @ms_flg: master mode flag.
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* @set_i2s_clk_rate: set I2S kernel clock rate
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* @put_i2s_clk_rate: put I2S kernel clock rate
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*/
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struct stm32_i2s_data {
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const struct regmap_config *regmap_conf;
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const struct stm32_i2s_conf *conf;
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struct regmap *regmap;
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struct platform_device *pdev;
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struct snd_soc_dai_driver *dai_drv;
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@ -249,8 +255,21 @@ struct stm32_i2s_data {
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unsigned int divider;
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unsigned int div;
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bool odd;
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bool i2s_clk_flg;
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int refcount;
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int ms_flg;
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int (*set_i2s_clk_rate)(struct stm32_i2s_data *i2s, unsigned int rate);
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void (*put_i2s_clk_rate)(struct stm32_i2s_data *i2s);
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};
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/**
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* struct stm32_i2s_conf - I2S configuration
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* @regmap_conf: regmap configuration pointer
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* @get_i2s_clk_parent: get parent clock of I2S kernel clock
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*/
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struct stm32_i2s_conf {
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const struct regmap_config *regmap_conf;
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int (*get_i2s_clk_parent)(struct stm32_i2s_data *i2s);
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};
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struct stm32_i2smclk_data {
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@ -261,6 +280,8 @@ struct stm32_i2smclk_data {
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#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
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static int stm32_i2s_get_parent_clk(struct stm32_i2s_data *i2s);
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static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
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unsigned long input_rate,
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unsigned long output_rate)
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@ -312,6 +333,33 @@ static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
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cgfr_mask, cgfr);
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}
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static bool stm32_i2s_rate_accurate(struct stm32_i2s_data *i2s,
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unsigned int max_rate, unsigned int rate)
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{
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struct platform_device *pdev = i2s->pdev;
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u64 delta, dividend;
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int ratio;
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if (!rate) {
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dev_err(&pdev->dev, "Unexpected null rate\n");
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return false;
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}
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ratio = DIV_ROUND_CLOSEST(max_rate, rate);
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if (!ratio)
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return false;
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dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));
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delta = div_u64(dividend, max_rate);
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if (delta <= STM32_I2S_CLK_RATE_TOLERANCE)
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return true;
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dev_dbg(&pdev->dev, "Rate [%u] not accurate\n", rate);
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return false;
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}
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static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
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unsigned int rate)
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{
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@ -332,6 +380,87 @@ static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
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return ret;
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}
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static void stm32_i2s_put_parent_rate(struct stm32_i2s_data *i2s)
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{
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if (i2s->i2s_clk_flg) {
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i2s->i2s_clk_flg = false;
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clk_rate_exclusive_put(i2s->i2sclk);
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}
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}
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static int stm32_i2s_set_parent_rate(struct stm32_i2s_data *i2s,
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unsigned int rate)
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{
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struct platform_device *pdev = i2s->pdev;
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unsigned int i2s_clk_rate, i2s_clk_max_rate, i2s_curr_rate, i2s_new_rate;
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int ret, div;
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/*
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* Set maximum expected kernel clock frequency
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* - mclk on:
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* f_i2s_ck = MCKDIV * mclk-fs * fs
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* Here typical 256 ratio is assumed for mclk-fs
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* - mclk off:
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* f_i2s_ck = MCKDIV * FRL * fs
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* Where FRL=[16,32], MCKDIV=[1..256]
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* f_i2s_ck = i2s_clk_max_rate * 32 / 256
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*/
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if (!(rate % STM32_I2S_RATE_11K))
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i2s_clk_max_rate = STM32_I2S_MAX_SAMPLE_RATE_11K * 256;
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else
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i2s_clk_max_rate = STM32_I2S_MAX_SAMPLE_RATE_8K * 256;
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if (!i2s->i2smclk)
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i2s_clk_max_rate /= 8;
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/* Request exclusivity, as the clock may be shared by I2S instances */
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clk_rate_exclusive_get(i2s->i2sclk);
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i2s->i2s_clk_flg = true;
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/*
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* Check current kernel clock rate. If it gives the expected accuracy
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* return immediately.
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*/
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i2s_curr_rate = clk_get_rate(i2s->i2sclk);
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if (stm32_i2s_rate_accurate(i2s, i2s_clk_max_rate, i2s_curr_rate))
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return 0;
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/*
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* Otherwise try to set the maximum rate and check the new actual rate.
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* If the new rate does not give the expected accuracy, try to set
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* lower rates for the kernel clock.
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*/
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i2s_clk_rate = i2s_clk_max_rate;
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div = 1;
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do {
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/* Check new rate accuracy. Return if ok */
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i2s_new_rate = clk_round_rate(i2s->i2sclk, i2s_clk_rate);
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if (stm32_i2s_rate_accurate(i2s, i2s_clk_rate, i2s_new_rate)) {
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ret = clk_set_rate(i2s->i2sclk, i2s_clk_rate);
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if (ret) {
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dev_err(&pdev->dev, "Error %d setting i2s_clk_rate rate. %s",
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ret, ret == -EBUSY ?
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"Active stream rates may be in conflict\n" : "\n");
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goto err;
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}
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return 0;
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}
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/* Try a lower frequency */
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div++;
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i2s_clk_rate = i2s_clk_max_rate / div;
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} while (i2s_clk_rate > rate);
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/* no accurate rate found */
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dev_err(&pdev->dev, "Failed to find an accurate rate");
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err:
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stm32_i2s_put_parent_rate(i2s);
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return -EINVAL;
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}
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static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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@ -635,12 +764,16 @@ static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
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clk_rate_exclusive_put(i2s->i2smclk);
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i2s->mclk_rate = 0;
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}
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if (i2s->put_i2s_clk_rate)
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i2s->put_i2s_clk_rate(i2s);
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return regmap_update_bits(i2s->regmap,
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STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, 0);
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}
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/* If master clock is used, set parent clock now */
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ret = stm32_i2s_set_parent_clock(i2s, freq);
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ret = i2s->set_i2s_clk_rate(i2s, freq);
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if (ret)
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return ret;
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ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
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@ -667,10 +800,11 @@ static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
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u32 cgfr;
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int ret;
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if (!(rate % 11025))
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clk_set_parent(i2s->i2sclk, i2s->x11kclk);
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else
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clk_set_parent(i2s->i2sclk, i2s->x8kclk);
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if (!i2s->mclk_rate) {
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ret = i2s->set_i2s_clk_rate(i2s, rate);
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if (ret)
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return ret;
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}
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i2s_clock_rate = clk_get_rate(i2s->i2sclk);
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/*
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@ -915,6 +1049,14 @@ static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
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clk_disable_unprepare(i2s->i2sclk);
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/*
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* Release kernel clock if following conditions are fulfilled
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* - Master clock is not used. Kernel clock won't be released trough sysclk
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* - Put handler is defined. Involve that clock is managed exclusively
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*/
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if (!i2s->i2smclk && i2s->put_i2s_clk_rate)
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i2s->put_i2s_clk_rate(i2s);
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spin_lock_irqsave(&i2s->irq_lock, flags);
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i2s->substream = NULL;
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spin_unlock_irqrestore(&i2s->irq_lock, flags);
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@ -1012,14 +1154,36 @@ static int stm32_i2s_dais_init(struct platform_device *pdev,
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return 0;
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}
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static const struct stm32_i2s_conf stm32_i2s_conf_h7 = {
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.regmap_conf = &stm32_h7_i2s_regmap_conf,
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.get_i2s_clk_parent = stm32_i2s_get_parent_clk,
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};
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static const struct stm32_i2s_conf stm32_i2s_conf_mp25 = {
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.regmap_conf = &stm32_h7_i2s_regmap_conf
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};
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static const struct of_device_id stm32_i2s_ids[] = {
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{
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.compatible = "st,stm32h7-i2s",
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.data = &stm32_h7_i2s_regmap_conf
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},
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{ .compatible = "st,stm32h7-i2s", .data = &stm32_i2s_conf_h7 },
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{ .compatible = "st,stm32mp25-i2s", .data = &stm32_i2s_conf_mp25 },
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{},
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};
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static int stm32_i2s_get_parent_clk(struct stm32_i2s_data *i2s)
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{
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struct device *dev = &i2s->pdev->dev;
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i2s->x8kclk = devm_clk_get(dev, "x8k");
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if (IS_ERR(i2s->x8kclk))
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return dev_err_probe(dev, PTR_ERR(i2s->x8kclk), "Cannot get x8k parent clock\n");
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i2s->x11kclk = devm_clk_get(dev, "x11k");
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if (IS_ERR(i2s->x11kclk))
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return dev_err_probe(dev, PTR_ERR(i2s->x11kclk), "Cannot get x11k parent clock\n");
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return 0;
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}
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static int stm32_i2s_parse_dt(struct platform_device *pdev,
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struct stm32_i2s_data *i2s)
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{
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@ -1031,8 +1195,8 @@ static int stm32_i2s_parse_dt(struct platform_device *pdev,
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if (!np)
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return -ENODEV;
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i2s->regmap_conf = device_get_match_data(&pdev->dev);
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if (!i2s->regmap_conf)
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i2s->conf = device_get_match_data(&pdev->dev);
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if (!i2s->conf)
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return -EINVAL;
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i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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@ -1052,15 +1216,18 @@ static int stm32_i2s_parse_dt(struct platform_device *pdev,
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return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
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"Could not get i2sclk\n");
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i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
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if (IS_ERR(i2s->x8kclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
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"Could not get x8k parent clock\n");
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if (i2s->conf->get_i2s_clk_parent) {
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i2s->set_i2s_clk_rate = stm32_i2s_set_parent_clock;
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} else {
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i2s->set_i2s_clk_rate = stm32_i2s_set_parent_rate;
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i2s->put_i2s_clk_rate = stm32_i2s_put_parent_rate;
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}
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i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
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if (IS_ERR(i2s->x11kclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
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"Could not get x11k parent clock\n");
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if (i2s->conf->get_i2s_clk_parent) {
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ret = i2s->conf->get_i2s_clk_parent(i2s);
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if (ret)
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return ret;
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}
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/* Register mclk provider if requested */
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if (of_property_present(np, "#clock-cells")) {
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@ -1126,7 +1293,7 @@ static int stm32_i2s_probe(struct platform_device *pdev)
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return ret;
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i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
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i2s->base, i2s->regmap_conf);
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i2s->base, i2s->conf->regmap_conf);
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if (IS_ERR(i2s->regmap))
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return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
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"Regmap init error\n");
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