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dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings

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Add bindings for the MediaTek External Memory Interface Interconnect,
which providers support system bandwidth requirements through Dynamic
Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.

This adds bindings for MediaTek MT8183 and MT8195 SoCs.

Note that this is modeled as a subnode of DVFSRC for multiple reasons:
 - Some SoCs have more than one interconnect on the DVFSRC (and two
   different kinds of EMI interconnect, and also a SMI interconnect);

 - Some boards will want to not enable the interconnect driver because
   some of those are not battery powered (so they just keep the knobs
   at full thrust from the bootloader and never care scaling busses);

 - Some DVFSRC interconnect features may depend on firmware.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240610085735.147134-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2024-06-10 10:57:30 +02:00 committed by Georgi Djakov
parent 1613e604df
commit 1a8009e108
3 changed files with 118 additions and 0 deletions
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51
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/mediatek,mt8183-emi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek External Memory Interface (EMI) Interconnect
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description: |
EMI interconnect providers support system bandwidth requirements through
Dynamic Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
The provider is able to communicate with the DVFSRC through Secure Monitor
Call (SMC).
ICC provider ICC Nodes
---- ----
_________ |CPU | |--- |VPU |
_____ | |----- ---- | ----
| |->| DRAM | ---- | ----
|DRAM |->|scheduler|----- |GPU | |--- |DISP|
| |->| (EMI) | ---- | ----
|_____|->|_________|---. ----- | ----
/|\ `-|MMSYS|--|--- |VDEC|
| ----- | ----
| | ----
| change DRAM freq |--- |VENC|
-------- | ----
SMC --> | DVFSRC | | ----
-------- |--- |IMG |
| ----
| ----
|--- |CAM |
----
properties:
compatible:
enum:
- mediatek,mt8183-emi
- mediatek,mt8195-emi
'#interconnect-cells':
const: 1
required:
- compatible
- '#interconnect-cells'
unevaluatedProperties: false

23
include/dt-bindings/interconnect/mediatek,mt8183.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021 MediaTek Inc.
* Copyright (c) 2024 Collabora Ltd.
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
#define SLAVE_DDR_EMI 0
#define MASTER_MCUSYS 1
#define MASTER_MFG 2
#define MASTER_MMSYS 3
#define MASTER_MM_VPU 4
#define MASTER_MM_DISP 5
#define MASTER_MM_VDEC 6
#define MASTER_MM_VENC 7
#define MASTER_MM_CAM 8
#define MASTER_MM_IMG 9
#define MASTER_MM_MDP 10
#endif

44
include/dt-bindings/interconnect/mediatek,mt8195.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2024 Collabora Ltd.
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
#define SLAVE_DDR_EMI 0
#define MASTER_MCUSYS 1
#define MASTER_GPUSYS 2
#define MASTER_MMSYS 3
#define MASTER_MM_VPU 4
#define MASTER_MM_DISP 5
#define MASTER_MM_VDEC 6
#define MASTER_MM_VENC 7
#define MASTER_MM_CAM 8
#define MASTER_MM_IMG 9
#define MASTER_MM_MDP 10
#define MASTER_VPUSYS 11
#define MASTER_VPU_0 12
#define MASTER_VPU_1 13
#define MASTER_MDLASYS 14
#define MASTER_MDLA_0 15
#define MASTER_UFS 16
#define MASTER_PCIE_0 17
#define MASTER_PCIE_1 18
#define MASTER_USB 19
#define MASTER_DBGIF 20
#define SLAVE_HRT_DDR_EMI 21
#define MASTER_HRT_MMSYS 22
#define MASTER_HRT_MM_DISP 23
#define MASTER_HRT_MM_VDEC 24
#define MASTER_HRT_MM_VENC 25
#define MASTER_HRT_MM_CAM 26
#define MASTER_HRT_MM_IMG 27
#define MASTER_HRT_MM_MDP 28
#define MASTER_HRT_DBGIF 29
#define MASTER_WIFI 30
#define MASTER_BT 31
#define MASTER_NETSYS 32
#endif