irqchip/armada-370-xp: Fix reenabling last per-CPU interrupt

The number of per-CPU interrupts is 29 (0 to 28). This is described by
the constant MPIC_MAX_PER_CPU_IRQS, set to 28 (the maximum per-CPU
interrupt).

Commit 0fa4ce746d ("irqchip/armada-370-xp: Re-enable per-CPU
interrupts at resume time") used the constant incorrectly in the
for-loop, it used the operator < instead of <=, causing it to iterate
only the first 28 interrupts (0 to 27), ignoring the last, 28th,
per-CPU interrupt.

To avoid this kind of confusions, fix this issue by renaming the constant
to MPIC_PER_CPU_IRQS_NR and set it to 29, the number of per-CPU IRQs.
Update its use in mpic_is_percpu_irq() accordingly.

Fixes: 0fa4ce746d ("irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time")
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: <stable+noautosel@kernel.org> # The 29th interrupt is not used in any device-tree
This commit is contained in:
Marek Behún 2024-08-07 18:41:01 +02:00 committed by Thomas Gleixner
parent 6abd809a54
commit 2793f68749

View File

@ -133,7 +133,7 @@
#define MPIC_INT_FABRIC_MASK 0x54
#define MPIC_INT_CAUSE_PERF(cpu) BIT(cpu)
#define MPIC_MAX_PER_CPU_IRQS 28
#define MPIC_PER_CPU_IRQS_NR 29
/* IPI and MSI interrupt definitions for IPI platforms */
#define IPI_DOORBELL_NR 8
@ -202,7 +202,7 @@ static inline bool mpic_is_ipi_available(struct mpic *mpic)
static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq)
{
return hwirq <= MPIC_MAX_PER_CPU_IRQS;
return hwirq < MPIC_PER_CPU_IRQS_NR;
}
/*
@ -545,7 +545,7 @@ static void mpic_smp_cpu_init(struct mpic *mpic)
static void mpic_reenable_percpu(struct mpic *mpic)
{
/* Re-enable per-CPU interrupts that were enabled before suspend */
for (irq_hw_number_t i = 0; i < MPIC_MAX_PER_CPU_IRQS; i++) {
for (irq_hw_number_t i = 0; i < MPIC_PER_CPU_IRQS_NR; i++) {
unsigned int virq = irq_linear_revmap(mpic->domain, i);
struct irq_data *d;