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irqchip/armada-370-xp: Fix reenabling last per-CPU interrupt
The number of per-CPU interrupts is 29 (0 to 28). This is described by the constant MPIC_MAX_PER_CPU_IRQS, set to 28 (the maximum per-CPU interrupt). Commit0fa4ce746d
("irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time") used the constant incorrectly in the for-loop, it used the operator < instead of <=, causing it to iterate only the first 28 interrupts (0 to 27), ignoring the last, 28th, per-CPU interrupt. To avoid this kind of confusions, fix this issue by renaming the constant to MPIC_PER_CPU_IRQS_NR and set it to 29, the number of per-CPU IRQs. Update its use in mpic_is_percpu_irq() accordingly. Fixes:0fa4ce746d
("irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time") Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: <stable+noautosel@kernel.org> # The 29th interrupt is not used in any device-tree
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@ -133,7 +133,7 @@
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#define MPIC_INT_FABRIC_MASK 0x54
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#define MPIC_INT_CAUSE_PERF(cpu) BIT(cpu)
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#define MPIC_MAX_PER_CPU_IRQS 28
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#define MPIC_PER_CPU_IRQS_NR 29
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/* IPI and MSI interrupt definitions for IPI platforms */
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#define IPI_DOORBELL_NR 8
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@ -202,7 +202,7 @@ static inline bool mpic_is_ipi_available(struct mpic *mpic)
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static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq)
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{
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return hwirq <= MPIC_MAX_PER_CPU_IRQS;
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return hwirq < MPIC_PER_CPU_IRQS_NR;
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}
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/*
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@ -545,7 +545,7 @@ static void mpic_smp_cpu_init(struct mpic *mpic)
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static void mpic_reenable_percpu(struct mpic *mpic)
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{
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/* Re-enable per-CPU interrupts that were enabled before suspend */
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for (irq_hw_number_t i = 0; i < MPIC_MAX_PER_CPU_IRQS; i++) {
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for (irq_hw_number_t i = 0; i < MPIC_PER_CPU_IRQS_NR; i++) {
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unsigned int virq = irq_linear_revmap(mpic->domain, i);
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struct irq_data *d;
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